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MTV512MV View Datasheet(PDF) - Myson Century Inc

Part Name
Description
Manufacturer
MTV512MV Datasheet PDF : 26 Pages
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MTV512M
Preliminary
=0
WslvA1I = 1
=0
WslvA2I = 1
=0
MbufI = 1
=0
Clears ReStaI flag.
No action.
Clears WslvA1I flag.
No action.
Clears WslvA2I flag.
No action.
Clears Master IIC bus interrupt flag (MbufI).
INTFLG (r) : Interrupt flag.
TXBI = 1 Indicates the TXBBUF need a new data byte, cleared by writing TXBBUF.
RCBI = 1 Indicates the RCBBUF has received a new data byte, cleared by reading RCBBUF.
SlvBMI = 1 Indicates the slave IIC address B match condition.
STOPI = 1 Indicates the slave IIC has detected a STOP condition for HSCL1/HSDA1 pins.
ReStaI = 1 Indicates the slave IIC has detected a repeat START condition for HSCL1/HSDA1
pins.
WslvA1I = 1 Indicates the slave A1 IIC has detected a STOP condition of write mode.
WslvA2I = 1 Indicates the slave A2 IIC has detected a STOP condition of write mode.
INTEN (w) : Interrupt enable.
ETXBI = 1 Enables TXBBUF interrupt.
ERCBI = 1 Enables RCBBUF interrupt.
ESlvBMI = 1 Enables slave address B match interrupt.
ESTOPI = 1 Enables IIC bus STOP interrupt.
EReStaI = 1 Enables IIC bus repeat START interrupt.
EWSlvA1I = 1 Enables slave A1 IIC bus STOP of write mode interrupt.
EWSlvA2I = 1 Enables slave A2 IIC bus STOP of write mode interrupt.
DDCCTRA1 (w) : DDC interface control register for HSCL1, HSDA1 pins.
DDC1en = 1 Enables DDC1 data transfer in DDC1 mode.
= 0 Disables DDC1 data transfer in DDC1 mode.
En128W = 1 The 128 bytes of DDCRAM1 can be written by IIC master.
= 0 The 128 bytes of DDCRAM1 cannot be written by IIC master.
Rev0 = 1 reserved
= 0 Normal operation.
Rev1 = 1 Normal operation.
= 0 reserved
SlvA1bs1,SlvA1bs0 : Slave IIC block A1's slave address length.
= 1,0 5-bit slave address.
= 0,1 6-bit slave address.
= 0,0 7-bit slave address.
SLVA1ADR (w) : Slave IIC block A1's enable and address.
EnslvA1= 1 Enables slave IIC block A1.
= 0 Disables slave IIC block A1.
page 16 of 16

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