MTV512MV View Datasheet(PDF) - Myson Century Inc
Part Name
Description
Manufacturer
MTV512MV Datasheet PDF : 26 Pages
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bit6-0 :
Slave IIC address A1 to which the slave block should respond.
RCBBUF (r) : Slave IIC block B receives data buffer.
TXBBUF (w) : Slave IIC block B transmits data buffer.
SLVBADR (w) : Slave IIC block B's enable and address.
ENslvB = 1 → Enables slave IIC block B.
= 0 → Disables slave IIC block B.
bit6-0 :
Slave IIC address B to which the slave block should respond.
CTRSLVB (r/w) :
Slave IIC block B's Control registers.
SlvBbs1,SlvBbs0 : Slave IIC block B's slave address length.
= 1,0 → 5-bit slave address.
= 0,1 → 6-bit slave address.
= 0,0 → 7-bit slave address.
SlavBa1 : Bit1 of received Slave B IIC address.
SlavBa0 : Bit0 of received Slave B IIC address.
DDCCTRA2 (w) : DDC interface control register for HSCL2, HSDA2 pins.
DDC1en = 1 → Enables DDC1 data transfer in DDC1 mode.
= 0 → Disables DDC1 data transfer in DDC1 mode.
En128W = 1 → The 128 bytes of DDCRAM2 can be written by IIC master.
= 0 → The 128 bytes of DDCRAM2 cannot be written by IIC master.
Rev0 = 1 → reserved
= 0 → Normal operation.
Rev1 = 1 → Normal operation.
= 0 → reserved
SlvA2bs1,SlvA2bs0 : Slave IIC block A2's slave address length.
= 1,0 → 5-bit slave address.
= 0,1 → 6-bit slave address.
= 0,0 → 7-bit slave address.
SLVA2ADR (w) : Slave IIC block A2's enable and address.
EnslvA2= 1 → Enables slave IIC block A2.
= 0 → Disables slave IIC block A2.
bit6-0 :
Slave IIC address A2 to which the slave block should respond.
MTV512M
Preliminary
A/D converter
The MTV512M is equipped with 4 VDD range 6-bit A/D converters. The ADC conversion range is from VSS to
VDD, S/W can select the current convert channel by setting the SADC1/SADC0 bit. The refresh rate for the
ADC is OSC freq./2304 (192us for 12MHz X'tal).
The ADC compares the input pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output
value is N when pin voltage is greater than VDD*N/64 and smaller than VDD*(N+1)/64.
Reg name
ADC
ADC
WDT
addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
F10h (w) ENADC
SADC3 SADC2 SADC1 SADC0
F10h (r)
ADC convert result
F18h (w) WEN WCLR
WDT2 WDT1 WDT0
page 17 of 17
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