KU80C51SL-AL View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

KU80C51SL-AL

8XC51SL/LOW VOLTAGE 8XC51SL KEYBOARD CONTROLLER

Intel 

8XC51SL LOW VOLTAGE 8XC51SL

PIN DESCRIPTIONS (Continued)

Table 1 Pin Descriptions (Continued)

Symbol Type

Description

XTAL1

I Input to the on-chip oscillator

XTAL2

O Output from the on-chip oscillator

AVGND

Analog ground potential

AVREF

Analog supply voltage nominally a5V g10% for 8XC51SL a3 3V g0 3V for Low

Voltage 8XC51SL

AIN0– 3

I A D Analog input channels

ADB0 –7 I O External address data bus Multiplexes the low-address byte and data during external

memory accesses

EAL VPP I External address input When held high the 51SL CPU executes out of internal Program

Memory unless the program counter exceeds 3FFFH When held low the 51SL CPU

always executes out of external memory EAL is latched on the falling edge of RST This

pin also receives the programming supply voltage (VPP) during EPROM programming

ALE

O Address Latch Enable output pulse latches the low address byte during external

memory access ALE is output at a constant rate of the oscillator frequency whether

or not there are accesses to external memory One ALE pulse is skipped during the

execution of a MOVX instruction ALE is disabled during Idle mode and can also be

disabled via Configuration register 1 control

PSENL

O Program Store Enable is the read strobe to external program memory PSENL is

qualified with RDL and A15 for use with an external Flash memory PSENL is not active

when the device executes out of internal program memory

MEMCSL I O External Memory Chip Select for code space address 4000H and above when EAL is

inactive (i e high) For EAL low MEMCSL is active Goes inactive during Idle mode and

Power-Down mode If external memory interfacing is not required MEMCSL can be

configured as a general purpose I O (controlled via Configuration register 1)

RST

I Resets the keyboard controller Hold RST high for two machine cycles

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