MU9C8248QEC View Datasheet(PDF) - Music Semiconductors

Part Name

Description

Manufacturer

MU9C8248QEC

FDDI SRT Interface

Music Semiconductors 

MU9C8248

BIT NAME

3

FITRENBL

2

FITRFILT

1

FSTRENBL

0

FSTRFILT

REGISTER SET DESCRIPTION (CONT’D)

DESCRIPTION

If FITRENBL is LOW, every Reserved for Implementer frame not containing an RIF is discarded. The

FDDI chipset is signalled to flush the frame. If FITRENBL is HIGH, the FITRFILT bit determines if the

frame is filtered or copied directly. If TBO is HIGH, filtering is also done on Reserved for Implementer

frames with an RIF.

If FITRFILT is LOW, the MU9C8248 signals the FDDI chipset to copy every Reserved for Implementer

frame not containing an RIF. If FITRFILT is HIGH the MU9C8248 checks the DA and forwards the frame

if the forwarding conditions are met, whether or not the frame contains an RIF.

If FSTRENBL is LOW, every Reserved for Future Standardization frame not containing an RIF is

discarded. The FDDI chipset is signalled to flush the frame. If FITRENBL is HIGH, the FITRFILT bit

determines if the frame is filtered or copied directly. If TBO is HIGH, filtering is also done on Reserved for

Future Standardization frames with an RIF.

If FSTRFILT is LOW, the MU9C8248 signals the MAC chip to copy every Reserved for Future

Standardization frame not containing an RIF. If FSTRFILT is HIGH, the MU9C8248 checks the DA and

forwards the frame if the forwarding conditions are met, whether or not the frame contains an RIF.

02H: Transparent Bridging/MAC Register

15 PONNE

14 DISGA

13 DISBA

12 DISFA

11 MLRN

10 LLRN

9

FILRN

8

FSLRN

7

XDAP

6

XSAP

5

XSRP

4

XABP

3

XDAL

2

XSAL

1

XSRL

0

XABL

If PONNE is LOW, the MU9C8248 performs negative filtering (Routine 0) for frames without an RIF, or

for all frames when TBO is HIGH. If PONNE is HIGH positive filtering is performed either on frame

without an RIF or on all frames.

If DISGA is LOW, all frames with a group address as DA and not containing an RIF (or all frames with a

group address as DA when TBO = HIGH) are filtered if PONNE is LOW. When DISGA is HIGH all

frames with group addresses are discarded. If PONNE is HIGH, this bit becomes “don't care”.

If DISBA is LOW, all frames with a DA containing a broadcast address and not containing an RIF (or all

frames with a DA containing a broadcast address when TBO = HIGH) are filtered when PONNE is also

programmed LOW. When DISBA is HIGH all frames with broadcast addresses are discarded. If PONNE

is set HIGH, this bit becomes “don't care”.

If DISFA is LOW, all frames with a functional address as DA and not containing an RIF (or all frames with

a functional address as DA when TBO = HIGH) are filtered when PONNE is made LOW. When DISFA is

HIGH all frames with functional addresses are discarded. If PONNE is HIGH, this bit becomes “don't

care”.

If MLRN is LOW, no learning of network addresses from MAC frames takes place. If this bit is set HIGH,

learning of addresses from MAC frames takes place by starting Routine 1 (if starting is enabled) and

placing new SA's in the FIFO, if the frame doesn't contain an RIF (or for all MAC frames if TBO or

LSASR is HIGH).

If LLRN is LOW, no learning of addresses from LLC frames takes place. If this bit is set HIGH, learning of

addresses from LLC frames takes place by starting Routine 1 (if starting is enabled) and placing new

SA's in the FIFO, if the frame doesn't contain an RIF (or for all LLC frames if TBO or LSASR is HIGH).

If FILRN is LOW, no learning of addresses from Reserved for Implementer frames takes place. If this bit

is HIGH, learning of addresses from reserved Reserved for Implementer frames takes place by starting

Routine 1 (if starting is enabled) and placing new SA's in the FIFO, if the frame doesn't contain an RIF

(or for all reserved type1 frames if TBO or LSASR is HIGH).

If FSLRN is LOW, no learning of addresses from Reserved for Future Standardization frames takes

place. If FSLRN is set HIGH, learning of addresses from Reserved for Future Standardization frames

takes place by starting Routine 1 (if starting is enabled) and placing new SA's in the FIFO, if the frame

doesn't contain an RIF (or for all Reserved for Future Standardization frames if TBO or LSASR is HIGH).

This bit determines the polarity of the XDAMAT output. If this bit is set HIGH the XDAMAT signal is

active HIGH. If XDAP is LOW, XDAMAT is active LOW.

This bit determines the polarity of the XSAMAT output. If this bit is set HIGH the XSAMAT signal is active

HIGH. If XSAP is LOW, XSAMAT is active LOW.

This bit determines the polarity of the SRMAT output. If this bit is set HIGH the SRMAT signal is active

HIGH. If XSRP is LOW, SRMAT is active LOW.

This bit determines the polarity of the ABORT output. If this bit is set HIGH the ABORT signal is active

HIGH. If XABP is LOW, ABORT is active LOW.

If this bit is LOW, XDAMAT is deasserted one DCLK period after it has been asserted. If this bit is HIGH,

XDAMAT is deasserted at the first Control symbol received.

If XSAL is LOW, XSAMAT is deasserted one DCLK period after it has been asserted. If this bit is HIGH,

XSAMAT is deasserted at the first Control symbol received.

If this bit is LOW, SRMAT is deasserted one DCLK period after it has been asserted. If this bit is HIGH,

SRMAT is deasserted at the first Control symbol received.

If XABL is LOW, ABORT is deasserted one DCLK period after it has been asserted. If XABL is HIGH,

ABORT is deasserted at the first Control symbol received.

Rev. 2.5 Web

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