MU9C8248QEC View Datasheet(PDF) - Music Semiconductors

Part Name

Description

Manufacturer

MU9C8248QEC

FDDI SRT Interface

Music Semiconductors 

MU9C8248

REGISTER SET DESCRIPTION (CONT’D)

BIT NAME

DESCRIPTION

1EH: Count Enable Register

15-14 Reserved

13 ENVOFR

12 ENSTMFR

11 ENMACFR

10 ENLLCFR

9

ENFIFR

8

ENFSFR

7-6 Reserved

5

ENVODA

4

ENSTMDA

3

ENMACDA

2

ENLLCDA

1

ENFIDA

0

ENFSDA

If ENVOFR is programmed HIGH, the frame counter is increased every time an VOID frame is received.

If ENSTMFR is programmed HIGH, the frame counter is increased every time an SMT frame with

address length 48 bits is received.

If ENMACFR is HIGH, the frame counter is increased every time an MAC frame with address length 48

bits is received.

If ENLLCFR is HIGH, the frame counter is increased every time an LLC frame with address length 48

bits is received.

If ENFIFR is programmed HIGH, the frame counter is increased every time a Reserved for Implementer

frame with address length 48 bits is received.

If ENFSFR is programmed HIGH, the frame counter is increased every time a Reserved for Future

Standardization frame with address length 48 bits is received.

When ENVODA is HIGH and if the VOID frame currently being received contains any data, the data

counter counts the number of data bytes in the frame. If ENVODA is LOW the data counter is not

increased when a VOID frame is being received.

When ENSTMDA is HIGH and if the Station Management frame with address length 48 bits, currently

being received contains any data, the data counter counts the number of data bytes in the frame. If

ENSTMDA is LOW the data counter is not increased when a Station Management frame is being

received.

When ENMACDA is HIGH and if the MAC frame with address length 48 bits, currently being received

contains any data, the data counter counts the number of data bytes in the frame. If ENMACDA is LOW

the data counter is not increased when a MAC frame is being received.

When ENLLCDA is HIGH and if the LLC frame with address length 48 bits, currently being received

contains any data, the data counter counts the number of data bytes in the frame. If ENLLCDA is LOW

the data counter is not increased when a LLC frame is being received.

When ENFIDA is HIGH and if the Reserved for Implementer frame with address length 48 bits, currently

being received contains any data, the data counter counts the number of data bytes in the frame. If

ENFIDA is LOW the data counter is not increased when a Reserved for Implementer frame is being

received.

When ENFSDA is HIGH and if the Reserved for Future Standardization frame with address length 48

bits, currently being received contains any data, the data counter counts the number of data bytes in the

frame. If ENFSDA is LOW the data counter is not increased when a Reserved for Future Standardization

frame is being received.

20H: LANCAM CWEC Register

15–0 CWEC15–0

Writing to this register starts a direct LANCAM access whereby the data written to CWEC15–0 is placed

on the DQ15–0 lines and /W, /CM and /EC are held LOW. If /INT is LOW, LANCAM access is prevented.

21H: LANCAM CREC Register

15–0 CREC15–0

Reading from this register starts a direct LANCAM access whereby the data read from CREC15–0 is

data placed on the DQ15–0 lines by the LANCAM. /CM and /EC are held LOW and /W is held HIGH for

this LANCAM cycle. If /INT is LOW, LANCAM access is prevented.

22H: LANCAM DWEC Register

15–0 DWEC15–0

Writing to this register starts a direct LANCAM access whereby the data written to DWEC15–0 is placed

on the DQ15–0 lines and /W and /EC are held LOW while /CM is held HIGH for this LANCAM cycle. If

/INT is LOW, LANCAM access is prevented.

23H: LANCAM DREC Register

15–0 DREC1–0

Reading from this register starts a direct LANCAM access whereby the data read from DREC15–0 is

data placed on the DQ15–0 lines by the LANCAM. /EC is held LOW and /W and /CM are held HIGH for

this LANCAM cycle. If /INT is LOW, LANCAM access is prevented.

Rev. 2.5 Web

18

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