BU9728 View Datasheet(PDF) - ROHM Semiconductor
Part Name
Description
Manufacturer
BU9728 Datasheet PDF : 24 Pages
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● Function description (BU9795AKV/AFV/AGUW)
○ Command and data transfer method
○ 3-SPI (3wire Serial interface)
This device is controlled by 3-wire signal (CSB, SCL, and SD).
First, Interface counter is initialized with CSB=“H",
and CSB=”L” makes SD and SCL input enable.
The protocol of 3-SPI transfer is as follows.
Each command starts with Command or Data judgment bit (D/C) as MSB data,
and continuously in order of D6 to D0 are followed after CSB =”L”.
(Internal data is latched at the rising edge of SCL, it converted to 8bits parallel data
at the falling edge of 8th CLK.)
Command
Command/Data
CSB
SCL
SD
D/C D6 D5 D4 D3 D2 D1 D0 D/C D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
D/C = “H” : Command D/C = “L” : Data
Fig. BU9795AKV /AFV /AGUW-10 3-SPI Command/Data transfer format
○Write display data and transfer method
* BU9795AKV
This LSI have Display Data RAM (DDRAM) of 35×4=140bit.
The relationship between data input and display data, DDRAM data and address are as follows.
Command
0000000 a b c d e f g h i j k l m n o p
…
Display Data
8 bit data will be stored in DDRAM. The address to be written is the address
specified by Address set command, and the address is automatically incremented in
every 4bit data.
Data can be continuously written in DDRAM by transmitting Data continuously.
(When RAM data is written successively after writing RAM data to 22h (SEG34),
the address is returned to 00h (SEG0) by the auto-increment function.
DDRAM address
00h 01h 02h 03h 04h 05h 06h 07h ・・・・・・・・ 1Eh 1Fh 20h 21h 22h
0a e i m q u
COM0
1b f j n r v
BIT 2 c
g
k
o
s
x
COM1
COM2
3d h l p t y
COM3
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
・・・・・・・・
SEG30 SEG31 SEG32 SEG33 SEG34
As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes
CSB=”L”→”H” before 4bits data transfer.
18/23
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