DF8064101211300SR0VY View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DF8064101211300SR0VY

Intel® Atom™ Processor D2000 and N2000 Series

Intel 

1.6

Clocking

• Differential Host clock of 100 MHz (HPL_CLKINP/HPL_CLKINN).

• Memory clocks - 100MHz differential for both DDR3-800 and DDR3-1066

— When running DDR3-800 or DDR3-1066, the 1x memory clocks is generated

from internal Host PLL and the 2x memory clock is generated from Memory PLL

• The differential DMI clock of 100 MHz (EXP_CLKINP/EXP_CLKINN) generates the

DMI core clock of 250 MHz.

• Display timings are generated from display PLLs that use a 96 MHz differential non-

SSC for VGA only, and 100 MHz differential clock with SSC or non-SSC as

reference.

• Host, Memory, DMI, Display PLLs and all associated internal clocks are disabled

until PWROK is asserted.

• The Display core clock Frequency by Skus

Table 1-2. The Display core clock Frequency by Skus

Display Core

Clock

Frequency/ MHz

D2500

355

D2550/

D2700

355

N2600

200

N2800

267

• 27 MHz crystal is needed to resolve digital display quality concerns.

Table 1-3. 27 MHz Requirement Range

Min/MHz

Nominal/

MHz

26.9919

27

Max/MHz

27.0081

Remark

300 ppm

Remark

1.7

Power Management

• PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3)

• SMRAM space remapping to A0000h (128 kB)

• Support extended SMRAM space above 256 MB, additional 1MB TSEG from the base

of graphics stolen memory (BSM) when enabled, and cacheable (cacheability

controlled by CPU).

• ACPI Rev 1.0b compatible power management

• Support CPU states: C0 and C1 (for D2000 series); C0-C4, C1E-C4E, Deep Power

Down Technology (code named C6)(for N2000 series)

• Support System states: S0, S3, S4 and S5

• Support CPU Thermal Management (TM1 & TM2) while D2000 series is TM1 only

Datasheet - Volume 1 of 2

13

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