DF8064101211300SR0VY View Datasheet(PDF) - Intel
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DF8064101211300SR0VY Datasheet PDF : 122 Pages
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2.2
System Memory Interface
Table 2-7. Memory Channel A
Signal Name
Description
Direction
DDR3_CK[3:0]
SDRAM and inverted Differential Clock: (3pairs per DIMM)
DDR3_CK#[3:0]
The differential clock pair is used to latch the command
into DRAM. Each pair corresponds to rank on DRAM side.
O
DDR3_CS#[3:0]
Chip Select: (1 per Rank). Used to qualify the command on
the command bus for a particular rank.
O
Clock Enable: (power management - 1 per Rank)
DDR3_CKE[3:0]
It is used during DRAM power up/power down and Self
O
refresh.
Multiplexed Address. Memory address bus for writing data
DDR3_MA[15:0]
to memory and reading data from memory. These signals
O
follow common clock protocol w.r.t. CK/CK# pairs
DDR3_BS[2:0]
Bank Select: These signals define which banks are selected
within each SDRAM rank
O
Write Enable Control Signal: Used with SA_WE# and
DDR3_RAS#
SA_CAS# (along with, control signal, SA_CS#) to define
O
the SDRAM Commands.
DDR3_CAS#
Write Enable Control Signal: Used with SA_WE# and
SA_CAS# (along with control signal, SA_CS#) to define the
O
SDRAM Commands.
DDR3_WE#
Write Enable Control Signal: Used with SA_WE# and
SA_CAS# (along with control signal, SA_CS#) to define the
O
SDRAM Commands.
Data Lines. Write Enable Control Signal: Used with
DDR3_DQ[63:0]
SA_WE# and SA_CAS# (along with control signal,
I/O
SA_CS#) to define the SDRAM Commands.
Write Enable Control Signal: Used with SA_WE# and
DDR3_DM[7:0]
SA_CAS# (along with control signal, SA_CS#) to define the
O
SDRAM Commands.
Data Strobes: SA_DQS[7:0] and its complement signal
group make up a differential strobe pair. The data is
DDR3_DQS[7:0]
captured at the crossing point of SA_DQS[8:0] and its
SA_DQS#[8:0] during read and write transactions. For
I/O
DDR3_DQS#[7:0] Read, the Strobe crossover and data are edge aligned,
whereas in the Write command, the strobe crossing is in
the centre of the data window.
DDR3_ODT[3:0]
ODT signal going to DRAM in order to turn ON the DRAM
ODT during Write.
O
Type
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
20
Datasheet - Volume 1 of 2
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