NT5CB128M8DN-CFI View Datasheet(PDF) - Nanya Technology
Part Name
Description
Manufacturer
NT5CB128M8DN-CFI Datasheet PDF : 138 Pages
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NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
2. After
is de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start
internal state initialization; this will be done independently of external clocks.
3. Clock (CK, ) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active.
Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a NOP or
Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered
“High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is finished,
including expiration of tDLLK and tZQinit.
4. The DDR3/L DRAM will keep its on-die termination in high impedance state as long as
is asserted. Further, the
DRAM keeps its on-die termination in high impedance state after
de-assertion until CKE is registered HIGH.
The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered
HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the
ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up
initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command
to load mode register. [tXPR=max (tXS, 5tCK)]
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1)
7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1)
8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable” command,
provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,
provide “High” to A8 and “Low” to BA0-BA2)
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3/L SDRAM is now ready for normal operation.
REV 1.2
May. 2011
CONSUMER DRAM
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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