NT5CB128M8DN-CFI View Datasheet(PDF) - Nanya Technology

Part Name

Description

Manufacturer

NT5CB128M8DN-CFI

1Gb DDR3 D-die SDRAM

Nanya Technology 

NT5CB128M8DN/NT5CB64M16DP

NT5CC128M8DN/NT5CC64M16DP

1Gb DDR3 D-die SDRAM

Register Definition

Programming the Mode Registers

For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the

DDR3/L SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As

the default values of the Mode Registers ( ) are not defined, contents of Mode Registers must be fully initialized and/or

re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be

altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the

user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be

redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which mean

these commands can be executed any time after power-up without affecting the array contents.

The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the

minimum time required between two MRS commands shown as below.

Fig. 6: tMRD Timing

The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset,

and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the

following figure.

REV 1.2

May. 2011

CONSUMER DRAM

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