NJU6433B View Datasheet(PDF) - Japan Radio Corporation

Part Name

Description

Manufacturer

NJU6433B

1/4 DUTY LCD DRIVER

Japan Radio Corporation  

NJU6433B

- Mode 5 : Shift Register 1~4 (D1~D200)

CE

SCL

DATA

MODE

1010

Mode Data

D1 2 3 4 5 6 7 8

194 195 196 197 198 199 200

Display Data x 200-bit

- Mode F : Shift Register 1~4 all “0”

CE

SCL

DATA

MODE

1111

Mode Data

Note 1) All of display data should be transmitted within 30ms to keep the display quality, because huge display

data D1 to D200 are transmitted at 4 times totally.

Note 2) Data is latched at the rising edge of the SCL.

Note 3) Mode data and display data are executed at the falling edge of the CE.

Note 4) In case of less than 4-bit data, the mode data remains the LSB side of the previous mode data.

Note 5) In case of over 4-bit data, the mode data is valid the previous 4-bit of the falling edge of the CE.

Note 6) In case of less than 50-bit data, the display data remains the last part of the previous display data.

Note 7) In case of over 50-bit data, the display data is valid the previous 50-bit of the falling edge of the CE.

(5) Initialization by Power On Reset

The NJU6433B incorporates the reset circuit of the detectable voltage type, and when the power supply is

turned on, it automatically initializes it (reset). When the VDD becomes 90% of the working voltage, the reset

signal is generated internally. Reset is completed after 2ms, and it becomes usually status. The serial data is

able to transmit after completed reset.

(5-1) Status of Power On Reset

1. Mode setting release (nonselective status)

2. Shift register : all “0”

3. Latch circuit : all “0”

90%

VDD

Internal reset signal

Usually status

Reset operation period (over 2ms)

Ver.2012-10-23

-7-

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