ADF7023BCPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADF7023BCPZ-RL
Analog Devices
ADF7023BCPZ-RL Datasheet PDF : 112 Pages
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ADF7023
Data Sheet
TIMING SPECIFICATIONS
VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, VGND = GND = 0 V, TA = TMIN to TMAX, unless otherwise noted.
Table 7. SPI Interface Timing
Parameter
Limit
t2
85
t3
85
t4
85
t5
170
t6
10
t7
5
t8
5
t9
85
t11
270
t12
310
t13
20
t14
20
Unit
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
µs typ
ns max
ns max
Test Conditions/Comments
CS low to SCLK setup time
SCLK high time
SCLK low time
SCLK period
SCLK falling edge to MISO delay
MOSI to SCLK rising edge setup time
MOSI to SCLK rising edge hold time
SCLK falling edge to CS hold time
CS high time
CS low to MISO high wake-up time, 26 MHz crystal with 7 pF load capacitance, TA = 25°C
SCLK rise time
SCLK fall time
Timing Diagrams
CS
t2 t3 t4
t5
t13
t14
t11
t9
SCLK
MISO
MOSI
BIT 7
t6
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7
t8
t7
7
6
5
4
3
2
1
0
7
Figure 2. SPI Interface Timing
BIT 0 X
BIT 7
7
CS
SCLK
t9
7
6
5
4
3
2
1
0
MISO
SPI STATE
t12
t6
X
SLEEP
WAKE UP
SPI READY
Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready T12 After Falling Edge of CS)
Rev. C | Page 16 of 112
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