ADF7023BCPZ-RL View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADF7023BCPZ-RL

High Performance, Low Power, ISM Band FSK/GFSK/OOK/MSK/GMSK Transceiver IC

Analog Devices 

ADF7023

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Data Sheet

CREGRF1 1

RBIAS 2

CREGRF2 3

RFIO_1P 4

RFIO_1N 5

RFO2 6

VDDBAT2 7

NC 8

ADF7023

TOP VIEW

(Not to Scale)

EPAD

24 CS

23 MOSI

22 SCLK

21 MISO

20 IRQ_GP3

19 GP2

18 GP1

17 GP0

NOTES

1. NC = NO CONNECT.

2. CONNECT EXPOSED PAD TO GND.

Figure 4. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic

1

CREGRF1

2

RBIAS

3

CREGRF2

4

RFIO_1P

5

RFIO_1N

6

RFO2

7

VDDBAT2

8

NC

9

CREGVCO

10

VCOGUARD

11

CREGSYNTH

12

CWAKEUP

13

XOSC26P

14

XOSC26N

15

DGUARD

16

CREGDIG1

17

GP0

18

GP1

19

GP2

20

IRQ_GP3

21

MISO

Function

Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

External Bias Resistor. A 36 kΩ resistor with 2% tolerance should be used.

Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

LNA Positive Input in Receive Mode. PA positive output in transmit mode with differential PA.

LNA Negative Input in Receive Mode. PA negative output in transmit mode with differential PA.

Single-Ended PA Output.

Power Supply Pin Two. Decoupling capacitors to the ground plane should be placed as close as

possible to this pin.

No Connect.

Regulator Voltage for the VCO. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

Guard/Screen for VCO. This pin should be connected to Pin 9.

Regulator Voltage for the Synthesizer. A 220 nF capacitor should be placed between this pin and

ground for regulator stability and noise rejection.

External Capacitor for Wake-Up Control. A 150 nF capacitor should be placed between this pin and

ground.

The 26 MHz reference crystal should be connected between this pin and XOSC26N. If an external

reference is connected to XOSC26N, this pin should be left open circuited.

The 26 MHz reference crystal should be connected between this pin and XOSC26P. Alternatively, an

external 26 MHz reference signal can be ac-coupled to this pin.

Internal Guard/Screen for the Digital Circuitry. Connect this pin to Pin 16, CREGDIG1.

Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this

pin and ground for regulator stability and noise rejection.

Digital GPIO Pin 0.

Digital GPIO Pin 1.

Digital GPIO Pin 2.

Interrupt Request, Digital GPIO Test Pin 3.

Serial Port Master In/Slave Out.

Rev. C | Page 18 of 112

Share Link: