W78354 View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

W78354

MONITOR MICROCONTROLLER

Winbond 

W78E354

FUNCTIONAL DESCRIPTION

A. 80C31 Core

The W78E354's 80C31 (CMOS MCU) core architecture consists of a CPU surrounded by various

Special Function Registers or SFRs. Some of these SFRs are standard 80C31 registers while others

are new additions, cf. Table 1. The device includes three general purpose I/O ports (P1, P2 and P3),

one output-only port (P4), 256 bytes of scratchpad RAM, two timer/counters (Timer0 and Timer1) and

one 8051 standard serial port. The processor supports 109 different instructions (without "MOVX

A,@DPTR" and "MOVX @DPTR,A") all of which are compatible with those of the MCS-51 family.

One distinguishing feature of the device architecture is the SFR address space into which all the

registers, peripherals and scratchpad RAM are mapped. Many of the instructions operate on an SFR

address rather than a specific register, greatly increasing the power of the instruction set.

The core controller has been designed around a state machine rather than utilizing a microcode

approach, a design methodology which offers several advantages. The first of these is that faster

circuits can be produced due to the fact that flip-flops are inherently faster than ROMs. Secondly, a

ROM-free approach allows the design to be directly utilized in ASIC gate array implementations, an

important factor for cost reductions. Finally, an entire digital logic approach provides better supply

noise immunity in most applications.

Table 1. W78E354's Special Function Registers (SFRs)

F8

FF

F0

+B

F7

E8

EF

E0

+ ACC

E7

D8

+ S1CON

S1STA

S1DAT

S1ADR

DF

D0

+ PSW

D7

C8 + CONTREG4

CF

C0

C7

B8

+ IP

SBRM0

SBRM1

PORT4

SOAREG

SOACLR

BF

B0

+ P3

ADC

INTVECT STATUS HFCOUNTL HFCOUNTH VFCOUNTL VFCOUNTH B7

A8

+ IE

SDAC7

SDAC8

SDAC9

SDAC10

SDAC11

SDAC12

SDAC13

AF

A0

+ P2

SDAC0

SDAC1

SDAC2

SDAC3

SDAC4

SDAC5

SDAC6

A7

98

+ SCON

SBUF

BSDAC0 BSDAC1

WDTCLR

DDAC0

DDAC1

DDAC2

9F

90

+ P1

AUTOLOAD DHREG

DVREG

DDC1

INTMSK

BDDAC

DBRM

97

88

+ TCON

TMOD

TL0

TL1

TH0

TH1

PARAL

PARAH

8F

80 + CONTREG1

SP

DPL

DPH

CONTREG5 CONTREG2 CONTREG3

PCON

87

Notes:

1. The SFRs with a "+" are both byte- and bit-addressable.

2. The registers in the shaded region are new additions to the 80C31 SFRs.

A.1 Address Space (cf. Figure 1)

The W78E354 CPU operates out of three separate address spaces:

- 11 -

Publication Release Date: April 1997

Revision A1

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