APA300-CQ View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
APA300-CQ Datasheet PDF : 174 Pages
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ProASICPLUS Flash Family FPGAs
DI <0:8>
WADDR <0:7>
WRB
WBLKB
WCLKS
WPE
SRAM
(256x9)
Sync Write
and
Sync Read
Ports
DO <0:8>
DI <0:8>
RADDR <0:7> WADDR <0:7>
RDB
RBLKB
RCLKS
RPE
WRB
WBLKB
WPE
SRAM
(256x9)
Async Write
and
Async Read
Ports
DO <0:8>
RADDR <0:7>
RDB
RBLKB
RCLKS
RPE
DI <0:8>
WADDR <0:7>
WRB
WBLKB
WCLKS
WPE
PARODD
SRAM
(256x9)
Sync Write
and
Async Read
Ports
DO <0:8>
DI <0:8>
RADDR <0:7> WADDR <0:7>
RDB
RBLKB
WRB
WBLKB
RPE
WPE
PARODD
SRAM
(256x9)
Async Write
and
Sync Read
Ports
DO <0:8>
RADDR <0:7>
RDB
RBLKB
RCLKS
RPE
PARODD
PARODD
Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
Figure 1-21 • Example SRAM Block Diagrams
Table 1-13 • Memory Block SRAM Interface Signals
SRAM Signal
Bits
In/Out
WCLKS
1
In
RCLKS
1
In
RADDR<0:7>
8
In
RBLKB
1
In
RDB
1
In
WADDR<0:7>
8
In
WBLKB
1
In
DI<0:8>
9
In
WRB
1
In
DO<0:8>
9
Out
RPE
1
Out
WPE
1
Out
PARODD
1
In
Note: Not all signals shown are used in all modes.
Description
Write clock used on synchronization on write side
Read clock used on synchronization on read side
Read address
Read block select (active Low)
Read pulse (active Low)
Write address
Write block select (active Low)
Input data bits <0:8>, <8> can be used for parity In
Write pulse (active Low)
Output data bits <0:8>, <8> can be used for parity Out
Read parity error (active High)
Write parity error (active High)
Selects Odd parity generation/detect when High, Even parity when Low
1-24
v5.7
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