DPL3520A View Datasheet(PDF) - Micronas
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DPL3520A Datasheet PDF : 56 Pages
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DPL 35xxA
PRELIMINARY DATA SHEET
2. Functional Description
In the following, the functional description of the
DPL 3520A is given. See section 13 for the modified
block diagrams of the DPL 3518A and DPL 3519A.
Block diagram: DPL 3520A consists of three blocks:
– analog input section containing channel selection and
2 high-quality A/D converters
– DSP section performing audio baseband
processing
– analog output section containing 6 D/A converters with
4-fold oversampling
Control-bus:
– The IC is controlled by I2C-bus. The I2C-bus device
addresses are 80hex/81hex, 84hex/85hex and
88hex/89hex.
Clock System:
– Single crystal clock system
(18.432 MHz), alternatively external clock.
Packages:
– 68-pin PLCC package
– 64-pin Shrink DIP package
– 52-pin Shrink DIP package
Power Consumption:
– typical: 450 mW at 5V
– typical: 120 mW at 8V
2.1. Features of the Analog Input Section
– three selectable analog pairs of audio baseband
inputs (+ three SCART inputs)
Input level: v2V RMS;
input impedance: w25 kΩ
– one selectable analog mono input;
Input level: v2V RMS;
input impedance: w10 kΩ
– 20 Hz to 20 kHz Bandwidth for SCART-to-SCART-
copy facilities
– two high-quality A/D converters
2.2. Features of the DSP-Section
– flexible selection of audio sources to be processed
– 4-channel digital input via I2S-Bus and 4-channel digi-
tal output via I2S-Bus.
– digital baseband processing: volume, bass, treble,
loudness on output channels 1 and 2.
– Dolby Pro Logic processing
– 100 Hz low-pass for subwoofer
– 30 ms delay line
A block diagram of the DSP software is shown in
Fig. 2–2.
Mono MONO_IN
SC1_IN_L
SCART1
SC1_IN_R
I2S_DA_OUT1 I2S_DA_OUT2 I2S_CL
I2S_DA_IN1
I2S_DA_IN2
I2S_WS
I2S Interface
I2S1/2L/R I2S1/2L/R
OUT1_L
D/A
OUT1_R
D/A
DSP
OUT2_L
D/A
OUT2_R
D/A
OUT1_L
OUT1_R
Channel 1
Output
OUT2_L
OUT2_R
Channel 2
Output
SC2_IN_L
SCART2
SC2_IN_R
A/D
SCART_L
SCART_L
D/A
A/D
SCART_R SCART_R
D/A
SC1_OUT_L
SCART 1
SC1_OUT_R
SC3_IN_L
SCART3
SC3_IN_R
SCART Switching Facilities
SC2_OUT_L
SCART 2
SC2_OUT_R
Fig. 2–1: Block diagram of the DPL 3520A
6
Micronas
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