LC78681KE, 78681KE-L
• JP three state output
MSB
LSB
10110110
10110111
Command
JP THREE STATE OUTPUT
JP TWO STATE OUTPUT (former scheme)
The JP three state output allows the track jump operation to be controlled from a single pin.
RES = low
○
• Track check mode
MSB
LSB
11110000
11111000
11111111
Command
TRACK COUNT IN
TRACK COUNT OUT
TWO BYTE COMMAND RESET
RES = low
○
The LC78681KE will count the specified number of tracks when the microprocessor sends an arbitrary binary
value in the range 16 to 254 after issuing either a track count in or a track count out command.
Note: 1. Once the desired track count has been input in binary, the track count operation is started by the fall of RWC.
2. During a track count operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required.
3. When a track count in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor
function to a track count monitor function. This signal goes high when the track count is half completed, and goes low when the count finishes.
The control microprocessor should monitor this signal for a low level to determine when the track count completes.
4. If a two-byte reset command is not issued, the track count operation will be repeated. That is, to skip over 20,000 tracks, issue a track count
200 command once, and then count the WRQ signal 100 times.
5. After performing a track count operation, use the brake command to have the pickup lock onto the track.
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