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ADF7021_06 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADF7021_06 Datasheet PDF : 44 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADF7021
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
Control Clock Input
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
CLKOUT Rise/Fall
CLKOUT Load
TEMPERATURE RANGE (TA)
POWER SUPPLIES
Voltage Supply
VDD
Transmit Current Consumption
0 dBm
10 dBm
0 dBm
10 dBm
Receive Current Consumption
Low Current Mode
High Sensitivity Mode
Power-Down Mode
Low Power Sleep Mode
Min
Typ
0.7 × V DD
DVDD − 0.4
−40
2.3
12.7
21
19.3
28
20
22
0.1
Max Unit
V
0.2 × V
VDD
±1 μA
10 pF
50 MHz
V
0.4 V
5
ns
10 pF
+85 °C
3.6 V
mA
mA
mA
mA
mA
mA
1
μA
1 For definition of frequency deviation, see the Register 2—Transmit Modulation Register section.
2 Measured as maximum unmodulated power. Output power varies with both supply and temperature.
3 For matching details, see the LNA/PA Matching section.
4 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.
5 See Table 8 for a description of different receiver modes.
6 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
Preliminary Technical Data
Test Conditions
IOH = 500 μA
IOL = 500 μA
All VDD pins must be tied together
VDD = 3.0 V, PA is matched into 50 Ω
FRF = 460 MHz
FRF = 460 MHz
FRF = 868 MHz
FRF = 868 MHz
Rev. PrI | Page 6 of 44

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