Peripheral operating requirements and behaviors
Table 16. SWD full voltage range electricals (continued)
Symbol
J3
Description
SWD_CLK clock pulse width
• Serial wire debug
Min.
Max.
Unit
20
—
ns
J4
SWD_CLK rise and fall times
J9
SWD_DIO input data setup time to SWD_CLK rise
J10
SWD_DIO input data hold time after SWD_CLK rise
J11
SWD_CLK high to SWD_DIO data valid
J12
SWD_CLK high to SWD_DIO high-Z
—
3
ns
10
—
ns
0
—
ns
—
32
ns
5
—
ns
SWD_CLK (input)
J2
J3
J3
J4
J4
Figure 4. Serial wire clock input timing
SWD_CLK
SWD_DIO
J11
SWD_DIO
J12
SWD_DIO
J11
SWD_DIO
J9
J10
Input data valid
Output data valid
Output data valid
Figure 5. Serial wire data timing
Kinetis KL27 With Up To 256 KB Flash, Rev3, 08/2014.
23
Freescale Semiconductor, Inc.