Peripheral operating requirements and behaviors
Table 22. Flash command timing specifications (continued)
Symbol Description
tersall
tvfykey
tersallu
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
Min.
Typ.
Max.
Unit
—
175
1300
ms
—
—
30
μs
—
175
1300
ms
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
Notes
2
1
2
3.4.1.3 Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors
Symbol Description
Min.
Typ.
Max.
Unit
IDD_PGM Average current adder during high voltage
—
flash programming operation
2.5
6.0
mA
IDD_ERS Average current adder during high voltage
—
flash erase operation
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 24. NVM reliability specifications
Symbol Description
tnvmretp10k
tnvmretp1k
nnvmcycp
Data retention after up to 10 K cycles
Data retention after up to 1 K cycles
Cycling endurance
Min.
Program Flash
5
20
10 K
Typ.1
50
100
50 K
Max.
—
—
—
Unit
years
years
cycles
Notes
—
—
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
28
Freescale Semiconductor, Inc.
Kinetis KL27 With Up To 256 KB Flash, Rev3, 08/2014.