IS43TR16256A(2012) View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

Manufacturer

IS43TR16256A
(Rev.:2012)

512Mx8, 256Mx16 4Gb DDR3 SDRAM

Integrated Silicon Solution 

IS43/46TR16256A, IS43/46TR16256AL,

IS43/46TR85120A, IS43/46TR85120AL

9.6 Data Setup, Hold and Slew Rate Derating

For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet

tDS(base) and tDH(base) value (see Table 72) to the ∆tDS and ∆tDH (see Table 73) derating value respectively. Example:

tDS (total setup time) = tDS(base) + ∆tDS.

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the

first crossing of V IH(ac) min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VREF(dc) and the first crossing of VIL(ac) max. If the actual signal is always earlier than the nominal slew rate

line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the

nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual

signal from the ac level to VREF(dc) level is used for derating value.

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc) max and

the first crossing of VREF(dc) . Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the

last crossing of VIH(dc) min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew

rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is

earlier than the nominal slew rate line anywhere between shaded ‘dc to V REF(dc) region’, the slew rate of a tangent line

to the actual signal from the dc level to VREF(dc) level is used for derating value.

For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)

at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac) .

For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

9.6.1 Data Setup and Hold Base-Values

Symbol

Reference

DDR3-800

tDS(base) AC175

VIH/L(ac)

75

tDS(base) AC150

VIH/L(ac)

125

tDH(base) DC100

VIH/L(dc)

150

DDR3-1066

25

75

100

DDR3-1333

-

30

65

DDR3-1600

-

10

45

Units

ps

ps

ps

Symbol

tDS(base) AC160

tDS(base) AC135

tDH(base) DC90

Reference

VIH/L(ac)

VIH/L(ac)

VIH/L(dc)

DDR3L-800

90

140

160

DDR3L-1066

40

90

110

NOTE: (ac/dc referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)

DDR3L-1333

-

45

75

DDR3L-1600

-

25

55

Units

ps

ps

ps

Integrated Silicon Solution, Inc. – www.issi.com –

73

Rev. 00A

11/14/2012

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