S25FL256SDSBFIQ01 View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

S25FL256SDSBFIQ01

MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

Spansion Inc. 

Data Sheet

2.2.2.3

Configuration Register Freeze Bit

The configuration register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior

generations. In the FL-S family it also locks the state of the configuration register TBPARM bit CR1[2],

TBPROT bit CR1[5], and the Secure Silicon Region (OTP) area.

2.2.2.4

Sector Erase Commands

The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.

The command for erasing a 4-kbyte sector is supported only in the 128-Mbit and 256-Mbit density FL-S

devices and only for use on the thirty two 4-kbyte parameter sectors at the top or bottom of the device

address space.

The erase command for 64-kbyte sectors are supported for the 128-Mbit and 256-Mbit density FL-S devices

when the ordering option for 4-kbyte parameter sectors with 64-kbyte uniform sectors are used. The 64-kbyte

erase command may be applied to erase a group of sixteen 4-kbyte sectors.

The erase command for a 256-kbyte sector replaces the 64-kbyte erase command when the ordering option

for 256-kbyte uniform sectors is used for the 128-Mbit and 256-Mbit density FL-S devices.

2.2.2.5

Deep Power Down

The Deep Power Down (DPD) function is not supported in FL-S family devices.

The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can

issue the former DPD command, to access a new bank address register. The bank address register allows

SPI memory controllers that do not support more than 24 bits of address, the ability to provide higher order

address bits for commands, as needed to access the larger address space of the 256-Mbit density FL-S

device. For additional information see Extended Address on page 54.

2.2.2.6

New Features

The FL-S family introduces several new features to SPI category memories:

 Extended address for access to higher memory density.

 AutoBoot for simpler access to boot code following power up.

 Enhanced High Performance read commands using mode bits to eliminate the overhead of SIO

instructions when repeating the same type of read command.

 Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher

clock rate read commands.

 DDR read commands for SIO, DIO, and QIO.

 Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to

the Advanced Sector Protection feature found in several other Spansion parallel interface NOR memory

families.

14

S25FL128S and S25FL256S

S25FL128S_256S_00_05 July 12, 2012

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