S25FL256SDSBFIQ01 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SDSBFIQ01
Cypress Semiconductor
S25FL256SDSBFIQ01 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Table 10.17 CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC DDR
Parameter Relative
Byte Address
Offset
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
Data
9Ah
2Ah
05h
08h
46h
43h
0Dh
0Eh
BDh
BEh
EDh
EEh
32h
03h
04h
01h
02h
02h
01h
03h
42h
00h
04h
02h
02h
04h
01h
06h
42h
01h
04h
04h
02h
05h
01h
07h
42h
02h
04h
05h
02h
06h
01h
08h
Description
Parameter ID (Latency Code Table)
Parameter Length (The number of following bytes in this parameter. Adding this value to the
current location value +1 = the first byte of the next parameter)
Number of rows
Row length in bytes
Start of header (row 1), ASCII “F” for frequency column header
ASCII “C” for Code column header
Read Fast DDR 3-byte address instruction
Read Fast DDR 4-byte address instruction
DDR Dual I/O Read 3-byte address instruction
DDR Dual I/O Read 4-byte address instruction
Read DDR Quad I/O 3-byte address instruction
Read DDR Quad I/O 4-byte address instruction
Start of row 2, SCK frequency limit for this row (50 MHz)
Latency Code for this row (11b)
Read Fast DDR mode cycles
Read Fast DDR latency cycles
DDR Dual I/O Read mode cycles
DDR Dual I/O Read latency cycles
Read DDR Quad I/O mode cycles
Read DDR Quad I/O latency cycles
Start of row 3, SCK frequency limit for this row (66 MHz)
Latency Code for this row (00b)
Read Fast DDR mode cycles
Read Fast DDR latency cycles
DDR Dual I/O Read mode cycles
DDR Dual I/O Read latency cycles
Read DDR Quad I/O mode cycles
Read DDR Quad I/O latency cycles
Start of row 4, SCK frequency limit for this row (66 MHz)
Latency Code for this row (01b)
Read Fast DDR mode cycles
Read Fast DDR latency cycles
DDR Dual I/O Read mode cycles
DDR Dual I/O Read latency cycles
Read DDR Quad I/O mode cycles
Read DDR Quad I/O latency cycles
Start of row 5, SCK frequency limit for this row (66 MHz)
Latency Code for this row (10b)
Read Fast DDR mode cycles
Read Fast DDR latency cycles
DDR Dual I/O Read mode cycles
DDR Dual I/O Read latency cycles
Read DDR Quad I/O mode cycles
Read DDR Quad I/O latency cycles
Document Number: 001-98283 Rev. *I
Page 131 of 144
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