A3V56S30ETP View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

A3V56S30ETP

256M Single Data Rate Synchronous DRAM

Unspecified 

A3V56S30ETP

A3V56S40ETP

256M Single Data Rate Synchronous DRAM

Write operation

Burst write or single write mode is selected

1. Burst write: A burst write operation is enabled by setting OPCODE A9 to 0. A burst write starts in the same clock as a write

command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4 and 8, like burst read operations.

The write start address is specified by the column address and the bank select address at the write command set cycle.

.

2. Single write: A single write operation is enabled by setting OPCODE A9 to 1. In a single write operation, data is only

written to the column address and the bank select address specified by the write command set cycle without regard to the

burst length setting. (The latency of data input is 0 clock).

Revision 2.2

Page 17/39

Mar., 2009

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