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ST72324J2-AUTO View Datasheet(PDF) - STMicroelectronics

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ST72324J2-AUTO Datasheet PDF : 194 Pages
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ST72324xx-Auto
Central processing unit (CPU)
Table 6. Arithmetic management bits (continued)
BIt Name
Function
Zero (Arithmetic Management bit)
1Z
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
t(s) 0 C
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.
duc Table 7. Software interrupt bits
ro BIt Name
Function
te P Software Interrupt Priority 1
le 5 I1
The combination of the I1 and I0 bits determines the current interrupt software priority
(see Table 8).
so Software Interrupt Priority 0
b 3 I0
The combination of the I1 and I0 bits determines the current interrupt software priority
O (see Table 8).
t(s) - Table 8. Interrupt software priority selection
c Interrupt software priority
du Level 0 (main)
ro Level 1
te P Level 2
leLevel 3 (= interrupt disable)
Level
Low
High
I1
I0
1
0
0
1
0
0
1
1
bso These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
O given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See Section 7: Interrupts on page 42 for more details.
Doc ID 13841 Rev 1
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