DSP1620 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP1620

DSP1627 Digital Signal Processor

Agere -> LSI Corporation 

Preliminary Data Sheet

February 1997

DSP1628 Digital Signal Processor

4 Hardware Architecture (continued)

Bit Manipulation Unit (BMU)

The BMU extends the DSP1600 core instruction set to

provide more efficient bit operations on accumulators.

The BMU contains logic for barrel shifting, normaliza-

tion, and bit field insertion/extraction. The unit also con-

tains a set of 36-bit alternate accumulators. The data in

the alternate accumulators can be shuffled with the data

in the main accumulators. Flags returned by the BMU

mesh seamlessly with the DSP1600 conditional instruc-

tions.

Error Correction Coprocessor (ECCP)

The ECCP performs full Viterbi decoding with instruc-

tions for MLSE equalization and convolutional decod-

ing. It is designed for 2-tap to 6-tap MLSE equalization

with Euclidean branch metrics and rate 1/1 to 1/6 con-

volutional decoding using constraint lengths from 2 to 7

with Euclidean or Manhattan branch metrics. Two vari-

ants of soft-decoded symbols, as well as hard-decoded

symbols may be programmed. The ECCP operates in

parallel with the DSP1600 core, increasing the through-

put rate. Single instruction Viterbi decoding provides

significant code compression required for single DSP

solutions in modern digital cellular applications. The

ECCP is the source of two interrupts and one flag to the

DSP1600 core.

Bit Input/Output (BIO)

The BIO provides convenient and efficient monitoring

and control of eight individually configurable pins. When

configured as outputs, the pins can be individually set,

cleared, or toggled. When configured as inputs, individ-

ual pins or combinations of pins can be tested for pat-

terns. Flags returned by the BIO mesh seamlessly with

conditional instructions.

Serial Input/Output Units (SIO and SIO2)

SIO and SIO2 offer asynchronous, full-duplex, double-

buffered channels that operate at up to 25 Mbits/s (for

20 ns instruction cycle in a nonmultiprocessor configu-

ration), and easily interface with other Lucent Technol-

ogies fixed-point DSPs in a multiple-processor

environment. Commercially available codecs and time-

division multiplex (TDM) channels can be interfaced to

the serial I/O ports with few, if any, additional compo-

nents. SIO2 is identical to SIO.

An 8-bit serial protocol channel may be transmitted in

addition to the address of the called processor in multi-

processor mode. This feature is useful for transmitting

high-level framing information or for error detection and

correction. SIO2 and BIO are pin-multiplexed with the

PHIF.

Lucent Technologies Inc.

9

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