DSP1620 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

DSP1620

DSP1627 Digital Signal Processor

Agere -> LSI Corporation 

DSP1628 Digital Signal Processor

4 Hardware Architecture (continued)

DSP 0

DSP 1

Preliminary Data Sheet

February 1997

DSP 7

DATA CHANNEL

CLOCK

ADDRESS/PROTOCOL CHANNEL

SYNC SIGNAL

Figure 6. Multiprocessor Communication and Connections

5 kΩ

VDD

5-4181 (F).a

4.8 Parallel Host Interface (PHIF)

The DSP1628 has an 8-bit parallel host interface for

rapid transfer of data with external devices. This parallel

port is passive (data strobes provided by an external

device) and supports either Motorola or Intel micro-

controller protocols. The PHIF also provides for 8-bit or

16-bit data transfers. As a flexible host interface, it re-

quires little or no glue logic to interface to other devices

(e.g., microcontrollers, microprocessors, or another

DSP).

The data path of the PHIF consists of a 16-bit input buff-

er, pdx0(in), and a 16-bit output buffer, pdx0(out). Two

output pins, parallel input buffer full (PIBF) and parallel

output buffer empty (POBE), indicate the state of the

buffers. In addition, there are two registers used to con-

trol and monitor the PHIF's operation: the parallel host

interface control register (phifc, see Table 32), and the

PHIF status register (PSTAT, see Table 8). The PSTAT

register, which reflects the state of the PIBF and POBE

flags, can only be read by an external device when the

PSTAT input pin is asserted. The phifc register defines

the programmable options for this port.

The function of the pins, PIDS and PODS, is program-

mable to support both the Intel and Motorola protocols.

The pin, PCSN, is an input that, when low, enables

PIDS and PODS (or PRWN and PDS, depending on the

protocol used). While PCSN is high, the DSP1628 ig-

nores any activity on PIDS and/or PODS. If a DSP1628

is intended to be continuously accessed through the

PHIF port, PCSN should be grounded. If PCSN is low

and their respective bits in the inc register are set, the

assertion of PIDS and PODS by an external device

causes the DSP1628 device to recognize an interrupt.

Programmability

The parallel host interface can be programmed for 8-bit

or 16-bit data transfers using bit 0, PMODE, of the phifc

register. Setting PMODE selects 16-bit transfer mode.

An input pin controlled by the host, PBSEL, determines

an access of either the high or low bytes. The assertion

level of the PBSEL input pin is configurable in software

using bit 3 of the phifc register, PBSELF. Table 7 sum-

marizes the port's functionality as controlled by the

PSTAT and PBSEL pins and the PBSELF and PMODE

fields.

For 16-bit transfers, if PBSELF is zero, the PIBF and

POBE flags are set after the high byte is transferred. If

PBSELF is one, the flags are set after the low byte is

transferred. In 8-bit mode, only the low byte is access-

ed, and every completion of an input or output access

sets PIBF or POBE.

Bit 1 of the phifc register, PSTROBE, configures the

port to operate either with an Intel protocol where only

the chip select (PCSN) and either of the data strobes

(PIDS or PODS) are needed to make an access, or with

a Motorola protocol where the chip select (PCSN), a

data strobe (PDS), and a read/write strobe (PRWN) are

needed. PIDS and PODS are negative assertion data

strobes while the assertion level of PDS is programma-

ble through bit 2, PSTRB, of the phifc register.

24

Lucent Technologies Inc.

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