CXD2434TQ View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXD2434TQ

Timing Generator for Progressive Scan CCD Image Sensor

Sony Semiconductor 

CXD2434TQ

4. Discharge of the vertical CCD

During EFS=L, the signal charges of the vertical CCD are discharge line by line. The IC detects the

transition from High to Low.

Note) See the detection timing for VD, TRIG, EFS and ESG.

<Discharge start>

Vertical CCD discharge is started in sync with HD input after the falling edge of EFS (Note). 3420 ns (81.4

ns x 42 clock pulses) are required to transfer one line vertically.

Note) See the detection timing for VD, TRIG, EFS and ESG.

<Discharge finish>

Since the operation uses 42 clock pulses as one unit, when the rising edge of EFS is detected in interval [n],

discharge operation stops from interval [n + 1].

Timing Chart 1

EFS

XV1

XV3

Timing Chart 2

n–1

n

n+1

n

n+1

CL

XV3

<Maximum number of dischargeable lines>

The number of lines transferred by discharge transfer and normal transfer during the following period should

not exceed 4096 lines.

Period: The period from when the XSG pin becomes low until XSG becomes low again or the TRIG pin

becomes low.

5. Internal logic stop (standby mode)

When the STDBY pin is set to low, clock supply is stopped to a part of the internal logic. However, output

from the oscillation cell (OSCI and OSCO pins) as well as the CL and CKO pins does not stop. The status

of each output pin when STDBY is low is shown below.

High:

XSUB, XSG

Low:

RG, H1, H2, XV1, XV2, XV3, XSHP, XSHD, XRS, XCPOB, XCPDM, PBLK, ID, WEN, BUSY,

CLD

Not stopped: OSCO, CL, CKO

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