DM9302 View Datasheet(PDF) - Davicom Semiconductor, Inc.

Part Name

Description

Manufacturer

DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

Davicom Semiconductor, Inc. 

DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

6.21 Receive Check Sum Control Status Register (32H)

Bit

Name

Default

Description

7

UDPS

HP0,RO UDP Checksum Status

1: UDP packet checksum is fail.

0: UDP packet checksum is OK or it is not a UDP packet.

6

TCPS

HP0,RO TCP Checksum Status

1: TCP packet checksum is fail.

0: TCP packet checksum is OK or it is not a TCP packet.

5

IPS

HP0,RO IP Checksum Status

1: IP packet checksum is ail

0: IP packet checksum is OK or it is not an IP packet.

4

UDPP

HP0,RO This is an UDP Packet

3

TCPP

HP0,RO This is a TCP Packet

2

IPP

HP0,RO This is an IP Packet

1

RCSEN HPS0,RW Receive Checksum Checking Enable

When set, the checksum status will store in packet first byte of status header.

0

DCSE HPS0,RW Discard Checksum Error Packet

When set, IP/TCP/UDP checksum field is error, this packet will be discarded.

6.22 uP Data Bus driving capability Register (38H)

Bit

Name

Default

Description

7

RESERVED 0,RW reserved

SD Bus Current Driving/Sinking Capability

00: 2mA

6:5 ISA_CURR P01,RW 01: 4mA (default)

10: 6mA

11: 8mA

4:3

Reserved P0,RW Reserved

Data Bus Output stepping

2

STEP

P0,RW 1: disabled

0: enabled

1

IOW_SPIKE

P0,RW

Eliminate IOW spike

1: eliminate about 2ns IOW spike

0

IOR_SPIKE

P1,RW

Eliminate IOR spike

1: eliminate about 2ns IOR spike

6.23 IRQ Pin Control Register (39H)

Bit

Name

Default

7:2 Reserved PS0,RO Reserved

IRQ Pin Output Type Control

1 IRQ_TYPE PET0,RW 1: IRQ Open-Collector output

0: IRQ direct output

IRQ Pin Polarity Control

0

IRQ_POL PET0,RW 1: IRQ active low

0: IRQ active high

Description

Preliminary datasheet

21

DM9302-15-DS-P01

July 30, 2009

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