DM9302 View Datasheet(PDF) - Davicom Semiconductor, Inc.

Part Name

Description

Manufacturer

DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

Davicom Semiconductor, Inc. 

DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

6.27 DSP PHY Control Register (58H~59H)

58H:

Bit

Name

Default

Description

7:0 DSP_CTL1 0,RW DSP Control Register 1 for testing only (register 58H)

59H:

Bit

7:0

Name

DSP_CTL2

Default

Description

0,RW DSP Control Register 2 for testing only (register 59H)

6.28 Per Port Control/Status Index Register (60H)

Bit

Name

Default

Description

7:5

reserved PHS0,RW reserved

4:2

reserved

0,RO reserved

1:0

INDEX PHS0,RW Port index for register 61H~84H

Write the port number to this register before write/read register 61H~84H.

Note: The processor port INDEX number is 3

6.29 Per Port Control Data Register (61H)

Bit

Name

Default

Description

7 RESERVED PE0,RW Reserved

6 PARTI_EN PE0,RW Enable Partition Detection

5 NO_DIS_RX PE0,RW Not Discard RX Packets when Ingress Bandwidth Control

When received packets bandwidth reach Ingress bandwidth threshold,

the packets over the threshold are not discarded but with flow control.

4 FLOW_DIS PE0,RW Flow control in full duplex mode, or back pressure in half duplex mode

enable

0: enable

1: disable

3 BANDWIDTH PE0,RW Bandwidth Control

0: Control with Ingress and Egress separately, ref to Register 66H.

1: Control with Ingress or Egress, ref to Register 67H

2

BP_DIS PE0,RW Broadcast packet filter

0: accept broadcast packets

1: reject broadcast packets

1

MP_DIS PE0,RW Multicast packet filter

0: accept multicast packets

1: reject multicast packets

0 MP_STORM PE0,RW Broadcast Storm Control

0: only broadcast packets storm are controlled

1: multicast packets also same as broadcast storm control.

Preliminary datasheet

23

DM9302-15-DS-P01

July 30, 2009

Share Link: