KAD2710L View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

KAD2710L

10-Bit, 275MSPS Analog-to-Digital Converter

Unspecified 

KAD2710L 10-Bit, 275MSPS Analog-to-Digital Converter

Functional Description

The KAD2710 is based upon a ten bit, 275MSPS A/D

converter in a pipelined architecture. The input volt-

age is captured by a sample & hold circuit and con-

verted to a unit of charge. Proprietary charge do-

main techniques are used to compare the input to a

series of reference charges. These comparisons de-

termine the digital code for each input value. The

converter pipeline requires 24 sample clocks to pro-

duce a result. Digital error correction is also applied,

resulting in a total latency of 28 clock cycles. This is

evident to the user as a latency between the start of

a conversion and the data being available on the

digital outputs.

At start-up, a self-calibration is performed to minimize

gain and offset errors. The reset pin (RST) is initially

held low internally at power-up and will remain in

that state until the calibration is complete. The clock

frequency should remain fixed during this time.

external reference voltage for the other chips in the

system. Additionally, an externally provided refer-

ence can be changed from the nominal value to

adjust the full-scale input voltage within a limited

range.

To select whether the full-scale reference is internally

generated or externally provided, the digital input

port VREFSEL should be set appropriately, low for in-

ternal or high for external. This pin also has an internal

18kΩ pull-up resistor. To use the internally generated

reference VREFSEL can be tied directly to AVSS, and

to use an external reference VREFSEL can be allowed

to float.

Analog Input

The fully differential ADC input (INP/INN) connects to

the sample and hold circuit. The ideal full-scale input

voltage is 1.5VPP, centered at the VCM voltage of

0.86V as shown in Figure 18.

Calibration accuracy is maintained for the sample

rate at which it is performed, and therefore should be

repeated if the clock frequency is changed by more

than 10%. Recalibration can be initiated via the RST

pin, or power cycling, at any time.

Reset

The KAD2710L resets and calibrates automatically on

power-up. To force a reset and initiate recalibration

of the ADC after power-up, connect an open-drain

output device to drive pin 28 (RST) and pull low for at

least ten sample clock periods. Do not use a device

with a pull-up on the reset pin, as it may prevent the

KAD2710 from properly executing the power-on re-

set.

Voltage Reference

The VREF pin is the full-scale reference, which sets the

full-scale input voltage for the chip and requires a

bypass capacitor of 0.1uF or larger. An internally

generated reference voltage is provided from a

bandgap voltage buffer. This buffer can sink or

source up to 50µA externally.

An external voltage may be applied to this pin to

provide a more accurate reference than the inter-

nally generated bandgap voltage or to match the

full-scale reference among a system of KAD2710L

chips. One option in the latter configuration is to use

one KAD2710L's internally generated reference as the

Figure 18. Analog Input Range

Best performance is obtained when the analog in-

puts are driven differentially in an ac-coupled con-

figuration. The common mode output voltage, VCM,

should be used to properly bias each input as shown

in Figures 19 and 20. An RF transformer will give the

best noise and distortion performance for wideband

and/or high intermediate frequency (IF) inputs. The

recommended biasing is shown in Figure 19.

Figure 19. Transformer Input

Rev 1.1

Page 12 of 17

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