HMP8154 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
HMP8154 Datasheet PDF : 34 Pages
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HMP8154, HMP8156A
BIT
NUMBER
7
6
5
4
3
2
1
0
FUNCTION
Software Reset
Power Down Enable
NTSC/PAL 2
Output Mode
Closed Caption
Line 21
Write Status
Closed Caption
Line 284
Write Status
NTSC/PAL 1
Output Mode
Y/G
Output Mode
C/B
Output Mode
TABLE 18. HOST CONTROL REGISTER
SUB ADDRESS = 0FH
DESCRIPTION
Setting this bit to “1” initiates a software reset. It is automatically reset to a “0” after the reset
sequence is complete.
0 = Normal operation
1 = Power down mode
0 = Enabled
1 = Disabled
0 = Caption_21A and Caption_21B data registers contain unused data
1 = Data has been output, host processor may now write to the registers
0 = Caption_284A and Caption_284B data registers contain unused data
1 = Data has been output, host processor may now write to the registers
0 = Enabled
1 = Disabled
0 = Enabled
1 = Disabled
0 = Enabled
1 = Disabled
RESET
STATE
0B
0B
0B
1B
1B
0B
0B
0B
BIT
NUMBER
FUNCTION
7-0
Line 21 Caption
Data
(First Byte)
BIT
NUMBER
7-0
FUNCTION
Line 21 Caption
Data
(Second Byte)
BIT
NUMBER
7-0
FUNCTION
Line 284 Caption
Data
(First Byte)
TABLE 19. CLOSED CAPTION_21A DATA REGISTER
SUB ADDRESS = 10H
DESCRIPTION
This register is cascaded with the closed caption_21B data register and they are read out
serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A
data register is shifted out first.
RESET
STATE
80H
TABLE 20. CLOSED CAPTION_21B DATA REGISTER
SUB ADDRESS = 11H
DESCRIPTION
This register is cascaded with the closed caption_21A data register and they are read out
serially as 16 bits during line 18, 21, or 22 if line 21 captioning is enabled. Bit D0 of the 21A
data register is shifted out first.
RESET
STATE
80H
TABLE 21. CLOSED CAPTION_284A DATA REGISTER
SUB ADDRESS = 12H
DESCRIPTION
This register is cascaded with the closed caption_284B data register and they are read out
serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the
284A data register is shifted out first.
RESET
STATE
80H
FN4343 Rev.5.00
August 20, 2009
Page 21 of 34
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