HMP8154 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
HMP8154 Datasheet PDF : 34 Pages
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HMP8154, HMP8156A
BIT
NUMBER
FUNCTION
7-0
Line 284 Caption
Data
(Second Byte)
BIT
NUMBER
FUNCTION
7-0
Assert BLANK
Output Signal
(Horizontal)
BIT
NUMBER
FUNCTION
7-2
Reserved
1-0
Assert BLANK
Output Signal
(Horizontal)
BIT
NUMBER
7-0
FUNCTION
Negate BLANK
Output Signal
(Horizontal)
TABLE 22. CLOSED CAPTION_284B DATA REGISTER
SUB ADDRESS = 13H
DESCRIPTION
This register is cascaded with the closed caption_284A data register and they are read out
serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the
284A data register is shifted out first.
RESET
STATE
80H
TABLE 23. START H_BLANK LOW REGISTER
SUB ADDRESS = 20H
DESCRIPTION
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1X clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This
register is ignored unless BLANK is configured as an output.
RESET
STATE
4AH
TABLE 24. START H_BLANK HIGH REGISTER
SUB ADDRESS = 21H
DESCRIPTION
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This
register is ignored unless BLANK is configured as an output.
TABLE 25. END H_BLANK REGISTER
SUB ADDRESS = 22H
DESCRIPTION
This 8-bit register specifies the horizontal count (in 1X clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000H. This register is ignored
unless BLANK is configured as an output.
RESET
STATE
000000B
11B
RESET
STATE
7AH
BIT
NUMBER
7-0
FUNCTION
Assert BLANK
Output Signal
(Vertical)
TABLE 26. START V_BLANK LOW REGISTER
SUB ADDRESS = 23H
DESCRIPTION
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
During SIF input mode, the register value (n) specifies the line number to start ignoring pixel
input data each noninterlaced input frame. The output video will be blanked starting on line
number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000H (note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
RESET
STATE
03H
FN4343 Rev.5.00
August 20, 2009
Page 22 of 34
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