CXD1803AR View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXD1803AR

CD-ROM DECODER

Sony Semiconductor 

CXD1803AQ/AR

Description of Functions

1. Pin Description

The pin description by function is given below.

1.1.CD player interface (5 pins)

This enables direct connection with the digital signal processor LSI for Sony's CD players. Digital signal

processor LSI for CD applications are hereafter called "CD DSP". See 2-1-1 for the data formats.

(1) DATA (DATA: input)

Serial data stream from CD DSP.

(2) BCLK (bit clock: input)

Bit clock signal; data signal strobe.

(3) LRCK (LR clock: input)

LR clock signal; indicates left and right channels of DATA signals.

(4) C2PO (C2 pointer: input)

C2 pointer signal; indicates that an error is contained in DATA input.

(5) EMP (emphasis: input)

Emphasis positive logic signal; indicates that emphasis has been applied to data from CD DSP.

1.2.Buffer memory interface (30 pins)

This is connected with a 32K-byte (256K-bit) or 128K-byte (1M-bit) standard SRAM; also connected with

256K-byte standard DRAM (two DRAMs of 128K-byte).

(1) XMWR (buffer memory write: output)

Data write strobe negative logic output signal to buffer memory.

(2) XMOE/XCAS (buffer memory output enable/column address strobe: output)

When connected to SRAM, data read strobe negative logic output signal to buffer memory.

When connected to DRAM, XCAS (column address strobe negative logic) signal.

(3) MA0 to 15 (buffer memory address: output)

Address signals to buffer memory. When connected to DRAM, MA0 to 8 are valid.

(4) MA16/XRAS (buffer memory address/row address strobe: output)

When connected to SRAM, address signal to buffer memory. XRAS (row address strobe negative

logic) signal when connected to DRAM.

(5) XME0, 1 (buffer memory chip enable: output)

When connected to a chip SRAM, chip enable negative logic signal to buffer memory. Not used when

connected to DRAM.

(6) MDB0 to 7, P (buffer memory data bus: bus)

Data bus signals to buffer memory; pulled up by standard 25kΩ resistor; MDBP pin is left open when

connected to an 8-bit/word SRAM.

(7) DRAM (buffer memory DRAM: input)

High is input when DRAM is connected as buffer memory.

Low is input when SRAM is connected as buffer memory.

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