1.3.Sub CPU interface (17 pins)
(1) XWR (sub CPU write: input)
Strobe negative logic input signal for writing IC internal register.
(2) XRD (sub CPU read: input)
Strobe negative logic input signal for reading IC internal register status.
(3) D0 to 7 (sub CPU data bus: input/output)
8-bit data bus.
(4) A0 to 4 (sub CPU address: input)
Address signal for selecting IC internal register from sub CPU.
(5) XINT (sub CPU interrupt: output)
Interrupt request negative logic signal to sub CPU.
(6) XCS (chip select: input)
IC select negative logic signal from sub CPU.
1.4.SCSI controller interface (13pins)
(1) SDRQ (SCSI data request: input)
DMA data request positive logic signal from SCSI controller IC.
(2) XSAC (SCSI DMA acknowledge: output)
DMA acknowledge negative logic signal to SCSI controller IC.
(3) XSWR (SCSI write: negative logic output)
Data write strobe output to SCSI controller IC.
(4) XSRD (SCSI read: negative logic output)
Data read strobe output to SCSI controller IC.
(5) SD0 to 7 (SCSI controller bus: input/output)
SCSI controller data bus signal.
1.5.DAC interface (4 pins)
The output format to DAC is shown in Fig. 1-1.
(1) BCKO (bit clock output: output)
Bit clock output signal to D/A converter.
(2) WCKO (word clock output: output)
Word clock output signal to D/A converter.
(3) LRCO (LR clock output: output)
LR clock output signal to D/A converter.
(4) DATO (data output: output)
Data output signal to D/A converter.
CXD1803AQ/AR
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