7C1325-100(2000) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

7C1325-100
(Rev.:2000)

256K x 18 Synchronous 3.3V Cache RAM

Cypress Semiconductor 

Timing Diagrams (continued)

ZZ Mode Timing [17, 18]

CLK

ADSP

ADSC

CE1

CE2

CE3

HIGH

LOW

HIGH

ZZ

ICC

I/Os

tZZS

ICC(active)

Three-state

ICCZZ

CY7C1325

tZZREC

Notes:

17. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.

18. I/Os are in three-state when exiting ZZ sleep mode.

15

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