MA82380 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

MA82380

HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS

Intel 

M82380

The M82380 DRAM Refresh Controller has the high-

est priority when requesting bus access and will in-

terrupt any active DMA process This allows large

blocks of data to be moved by the DMA controller

without affecting the refresh function Also the DMA

controller is not required to completely relinquish the

bus the refresh controller simply steals a bus cycle

between DMA accesses

The amount by which the refresh address is incre-

mented is programmable to allow for different bus

widths and memory bank arrangements

1 1 6 CPU RESET FUNCTION

The M82380 contains a special reset function which

can respond to hardware reset signals from the

M82384 as well as a software reset command The

circuit will hold the i386 processor’s RESET line ac-

tive while an external hardware reset signal is pres-

ent at its RESET input It can also reset the i386

processor as the result of a software command The

software reset command causes the M82380 to

hold the processor’s RESET line active for a mini-

mum of 62 CLK2 cycles enough time to allow an

M80386 to re-initialize

The M82380 can be programmed to sense the shut-

down detect code on the status lines from the

M80386 If the Shutdown Detect function is enabled

the M82380 will automatically reset the processor A

diagnostic register is available which can be used to

determine the cause of reset

1 1 7 REGISTER MAP RELOCATION

After a hardware reset the internal registers of the

M82380 are located in I O space beginning at port

address 0000H The map of the M82380’s registers

is relocatable via a software command The default

mapping places the M82380 between I O address-

es 0000H and 00DBH The relocation register allows

this map to be moved to any even 256-byte bounda-

ry in the processor’s 16-bit I O address space or any

even 16-Mbyte boundary in the 32-bit memory ad-

dress space

1 2 Host Interface

The M82380 is designed to operate efficiently on the

local bus of an M80386 microprocessor The control

signals of the M82380 are identical in function to

those of the i386 processor As a slave the M82380

operates with all of the features available on the

i386 processor bus When the M82380 is in the Mas-

ter Mode it looks identical to the i386 processor to

the connected devices

The M82380 monitors the bus at all times and de-

termines whether the current bus cycle is a pipelined

or non-pipelined access All of the status signals of

the processor are monitored

The control status and data registers within the

M82380 are located at fixed addresses relative to

each other but the group can be relocated to either

memory or I O space and to different locations with-

in those spaces

As a Slave device the M82380 monitors the con-

trol status lines of the CPU The M82380 will gener-

ate all of the wait states it needs whenever it is ac-

cessed This allows the programmer the freedom of

accessing M82380 registers without having to insert

NOPs in the program to wait for slower M82380 in-

ternal registers

The M82380 can determine if a current bus cycle is

a pipelined or a non-pipelined cycle It does this by

monitoring the ADS and READY signals and thereby

keeping track of the current state of the i386 proces-

sor

As a bus master the M82380 looks like an i386

processor to the rest of the system This enables the

designer greater flexibility in systems which include

the M82380 The designer does not have to alter the

interfaces of any peripherals designed to operate

with the i386 processor to accommodate the

M82380 The M82380 will access any peripherals on

the bus in the same manner as the i386 processor

including recognizing pipelined bus cycles

The M82380 is accessed as an 8-bit peripheral This

is done to maintain compatibility with existing system

architectures and software The i386 processor

places the data of all 8-bit accesses either on D (0 –

7) or D (8 – 15) The M82380 will only accept data on

these lines when in the Slave Mode When in the

Master Mode the M82380 is a full 32-bit machine

sending and receiving data in the same manner as

the i386 processor

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