P87CL881H View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

P87CL881H

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM / LQFP44 Package

Philips Electronics 

Philips Semiconductors

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

Product specification

P87CL881H

6.5 Oscillator circuitry

General information on the oscillator circuitry can be found

in the “TELX family” data sheet.

6.5.1 RESONATOR REQUIREMENTS

For correct function of the oscillator, the values

of R1 and C0 of the chosen resonator (quartz or PXE) must

be below the line shown in Fig.6a. The value of the parallel

resistor R0 must be less than 47 kΩ. The wiring between

chip and resonator should be kept as short as possible.

handboo5k,0h0alfpage

R1

(Ω)

400

300

(1) (2) (3)

200

100

0

0

20

40

MDA088

60 Co (pF) 80

6.6 Non-conformance

6.6.1 PROGRAMMING INTERFACE/TRANSPARENT MODE

The transparent mode is a special operating mode of the

microcontroller used for parallel and In-System OTP

programming.

For certain combinations of data written to Port 2 (used for

control signal during parallel programming mode) the

Transparent mode may be incorrectly active during normal

operation of the microcontroller. In this case, a transition

on any of the Port 0 pins can influence the read out of the

on-chip program memory resulting in incorrect code

execution.

To avoid this problem, the InSysMode bit in the OTP

In-System Programming Register (SFR address DCH)

must be set in the start-up sequence of the program code.

Apart from preventing incorrect operation as described

above, the setting of this bit does not affect the normal

operation.

6.6.2 MOVC INSTRUCTION LIMITATION

The ‘MOVC’ access to a data or program byte stored in

internal ROM/OTP-memory is inhibited while fetching

code from external program memory in roll-over mode.

Roll-over mode means that the CPU executes code out of

the external program memory because the program

counter exceeds the highest address for internal program

memory. The affected address range is FC00H to FFFFH.

C1e and C2e are the external load capacitances; normally not needed

due to integrated load capacitances of typically 10 pF.

(1) C1e = C2e = 22 pF.

(2) C1e = C2e = 0 pF.

(3) C1e = C2e = 12 pF.

a. Resonator curves for 3.58 MHz.

handbook, halfpage

C1 L1

R0

C0

R1

MGL137

6.6.3 LOW VOLTAGE DETECTION

The LVDI bit (LVDCON.6) may be incorrectly set due to a

glitch on the LVD output when the LVD is enabled by

changing the bits LVDCON<3:0> from ‘0000’ to any value

within the range ‘0001’ to ‘0101’. If bit EA in register IEN0

is enabled, an unwanted interrupt may occur.

A software workaround for this problem exist. During the

initialisation sequence:

• Enable LVD by writing to register LVDCON

• Enable LVD interrupt by writing to register IEN2

• Clear the LVDI bit by writing to LVDCON a second time

• Set bit EA in register IEN0 (ensures LVDI to be cleared

after initialisation).

b. Resonator equivalent circuit.

Fig.6 Resonator requirements for the ACO.

1999 Apr 16

17

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