APA3160A View Datasheet(PDF) - Anpec Electronics
Part Name
Description
Manufacturer
APA3160A Datasheet PDF : 38 Pages
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APA3160A
Function Description (Cont.)
Initialization Sequence
Use the following sequence to power-up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V.
2. Initialize digital inputs and PVDD supply as following:
•Drive RST=0, SD=1, and other digital inputs to their desired state while ensuring that all are never more than 2.5V
above AVDD/DVDD. Provide stable and valid I2S clocks (MCLK, LRCLK, and SCLK). Wait at least 100µs, drive
RST=1, and wait at least another 13.5ms.
• Ramp up PVDD to at least 8V while ensuring that it remains below 6V for at least 100µs after AVDD/DVDD reaches
3V. Then wait at least another 10µs.
3. Configure the DAP via I2C (see Users’s Guide for typical values): biquads (0x29-36)DRC parameters (0x3A-3C,
0x40-42, and 0x46) Bank select (0x50).
4. Configure remaining registers.
5. Exit shutdown (sequence defined below).
Normal Operation
The following are the only events supported during normal operation:
(a) Writes to master/channel volume registers
(b) Writes to soft mute register
(c) Enter and exit shutdown (sequence defined below)
(d) Clock errors and rate changes
Note: Events (c) and (d) are not supported for 240ms+1.3xt0 0 after trim following AVDD/DVDD power up ramp (where Tstart is
specified by register 0x1A).
Shutdown Sequence
Enter:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x40 to register 0x05.
3. Wait at least 1ms+1.3xtstop (where tstop is specified by register 0x1A).
4. Once in shutdown, stable clocks are not required while device remains idle.
5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before returning to step
4 of initialization sequence.
Exit:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms after trim following
AVDD/DVDD powerup ramp).
3. Wait at least 1ms+1.3xtstart (where tstart is specified by register 0x1A).
4. Proceed with normal operation.
Copyright © ANPEC Electronics Corp.
20
Rev. A.6 - Jan., 2013
www.anpec.com.tw
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