APA3160A View Datasheet(PDF) - Anpec Electronics

Part Name

Description

Manufacturer

APA3160A

20W Stereo Digital Class-D Audio Power Amplifier

Anpec Electronics 

APA3160A

Function Description (Cont.)

Error Status Register (0x02)

The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register

(write zeroes) and then read them to determine if they are persistent errors. Error Definitions:

MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.

SCLK Error: The number of SCLKs per LRCLK is changing.

LRCLK Error: LRCLK frequency is changing.

Table 4. Error Status Register (0x02)

D7 D6 D5 D4 D3 D2 D1 D0

FUNCTION

1

-

-

-

-

-

-

- MCLK error

-

1

-

-

-

-

-

- PLL auto clock error

-

-

1

-

-

-

-

- SCLK error

-

-

-

1

-

-

-

- LRCLK error

-

-

-

-

1

-

-

- Reserved

-

-

-

-

-

1

-

- Reserved

-

-

-

-

-

-

0

-

Over-Current (OC) or Under-Voltage (UVP) or Over-Temperature

(OTP) warning

-

-

-

-

-

-

-

1

Over-temperature warning (sets around 145OC) POR error, OCP,

thermal shutdown error

0

0

0

0

0

0

0

0 No errors

System Control Register 1 (0x03)

The system control register 1 has several functions:

Bit D7: If 0, the dc-blocking filter for each channel is disabled. If 1, the dc-blocking filter ( -3dB cutoff < 1Hz ) for each

channel is enabled (default).

Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes same time as volume

ramp defined in reg 0x0E. If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single

step volume ramp Bits D1-D0: Select de-emphasis.

Table 5. System Control Register 1 (0x03)

D7 D6 D5 D4 D3 D2 D1 D0

FUNCTION

0

-

-

-

-

-

-

- PWM high-pass (dc blocking) disenabled

1

-

-

-

-

-

-

- PWM high-pass (dc blocking) enabled

-

0

-

-

-

-

-

- Reserved

-

-

0

-

-

-

-

- Reserved

-

-

-

0

-

-

-

- Reserved

-

-

-

-

0

-

-

- Reserved

-

-

-

-

-

0

-

- Reserved

-

-

-

-

-

-

0

0 No de-emphasis

-

-

-

-

-

-

0

1 Reserved

-

-

-

-

-

-

1

0 De-emphasis for fS=44.1kHz

-

-

-

-

-

-

1

1 De-emphasis for fS=48kHz

Copyright © ANPEC Electronics Corp.

23

Rev. A.6 - Jan., 2013

www.anpec.com.tw

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