APA3160A View Datasheet(PDF) - Anpec Electronics
Part Name
Description
Manufacturer
APA3160A Datasheet PDF : 38 Pages
| |||
APA3160A
Function Description (Cont.)
Volume Configuration Register (0x0E) (Cont.)
Table 11. Volume Control Register (0x0E)
D7 D6 D5 D4 D3 D2 D1
-
-
-
-
-
1
0
-
-
-
-
-
1
1
-
-
-
-
-
1
1
D0
1 Reserved
0 Reserved
1 Volume slew 0 step
FUNCTION
Modulation Limit Register (0x10)
Table 12. Modulation Limit Register (0x10)
D7 D6 D5 D4 D3 D2 D1 D0
-
-
-
-
-
0
0
0
-
-
-
-
-
0
0
1
-
-
-
-
-
0
1
0
-
-
-
-
-
0
1
1
-
-
-
-
-
1
0
0
-
-
-
-
-
1
0
1
-
-
-
-
-
1
1
0
-
-
-
-
-
1
1
1
0
0
0
0
0
-
-
-
MODULATION LIMIT
Reserved
98.4%
97.7%
96.9%
96.1%
95.3%
94.5%
93.8%
Reserved
Start/Stop Period Register (0x1A)
This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down
command or change in the SD state. This helps to reduce pops and clicks at start-up and shutdown. The times are
only approximate and vary depending on device activity level and I2S clock stability.
Table 13. Start/Stop Period Register (0x1A)
D7 D6 D5 D4 D3 D2 D1 D0
FUNCTION
0
0
0
-
-
-
-
- Reserved
-
-
-
0
0
-
-
- Reserved
-
-
-
0
1
0
0
0 16.5ms 50% duty cycle start/stop period
-
-
-
0
1
0
0
1 23.9ms 50% duty cycle start/stop period
-
-
-
0
1
0
1
0 31.4ms 50% duty cycle start/stop period
-
-
-
0
1
0
1
1 40.4ms 50% duty cycle start/stop period
-
-
-
0
1
1
0
0 53.9ms 50% duty cycle start/stop period
-
-
-
0
1
1
0
1 70.3ms 50% duty cycle start/stop period
-
-
-
0
1
1
1
0 94.2ms 50% duty cycle start/stop period
-
-
-
0
1
1
1
1 125.7ms 50% duty cycle start/stop period
Copyright © ANPEC Electronics Corp.
26
Rev. A.6 - Jan., 2013
www.anpec.com.tw
Share Link: 