ATMEGA161 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA161 Datasheet PDF : 134 Pages
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Power-on Reset
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is nominally 1.4V (rising
VCC). The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up
reset, as well as detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold
voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after VCC rise. The
time-out period of the delay counter can be defined by the user through the CKSEL fuses. The eight different selections for
the delay period are presented in Table 4. The RESET signal is activated again, without any delay, when the VCC
decreases below detection level.
Figure 25. MCU Start-up, RESET Tied to VCC.
VCC
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL
RESET
Figure 26. MCU Start-up, RESET Controlled Externally
VCC
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL
RESET
External Reset
An external reset is generated by a low level on the RESET pin. Reset pulses longer than 500 ns will generate a reset,
even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage – VRST on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has
expired.
26
ATmega161(L)
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