ATMEGA161 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA161 Datasheet PDF : 134 Pages
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General Interrupt Flag Register – GIFR
Bit
7
6
5
4
$3A ($5A)
INTF1 INTF0
INTF2
-
Read/Write
R/W
R/W
R/W
R
Initial value
0
0
0
0
3
2
1
0
-
-
-
-
GIFR
R
R
R
R
0
0
0
0
• Bit 7 - INTF1: External Interrupt Flag1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $004. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 6 - INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 5 - INTF2: External Interrupt Flag2
When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one). If the I-bit in SREG and the INT2 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $006. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 4..0 - Res: Reserved bits
These bits are reserved bits in the ATmega161 and always read as zero.
Timer/counter Interrupt Mask Register – TIMSK
Bit
$39 ($59)
Read/Write
Initial value
7
TOIE1
R/W
0
6
OCIE1A
R/W
0
5
OCIE1B
R/W
0
4
TOIE2
R/W
0
3
TICIE1
R/W
0
2
OCIE2
R/W
0
1
TOIE0
R/W
0
0
OCIE0
R/W
0
TIMSK
• Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is
enabled. The corresponding interrupt (at vector $012) is executed if an overflow in Timer/Counter1 occurs, i.e., when the
TOV1 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 6 - OCE1A:Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match
interrupt is enabled. The corresponding interrupt (at vector $00e) is executed if a CompareA match in Timer/Counter1
occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 5 - OCIE1B:Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match
interrupt is enabled. The corresponding interrupt (at vector $010) is executed if a CompareB match in Timer/Counter1
occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 4 - TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is
enabled. The corresponding interrupt (at vector $00a) is executed if an overflow in Timer/Counter2 occurs, i.e., when the
TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event
Interrupt is enabled. The corresponding interrupt (at vector $00C) is executed if a capture-triggering event occurs on pin 31,
ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 2 - OCIE2:Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match inter-
rupt is enabled. The corresponding interrupt (at vector $008) is executed if a Compare2 match in Timer/Counter2 occurs,
i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
30
ATmega161(L)
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