ADSP-21160NCBZ-100(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21160NCBZ-100
(Rev.:RevD)

SHARC Digital Signal Processor

Analog Devices 

ADSP-21160M/ADSP-21160N

Reset

For reset, see Table 14 and Figure 11.

Table 14. Reset

Parameter

Min

Max

Unit

Timing Requirements

tWRST

RESET Pulsewidth Low1

tSRST

RESET Setup Before CLKIN High2

4tCK

ns

8

ns

1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

2 Only required if multiple ADSP-21160x DSPs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple

ADSP-21160x DSPs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.

CLKIN

RESET

tW R ST

Figure 11. Reset

tSRST

Rev. D | Page 23 of 58 | September 2015

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