ADSP-21160NCBZ-100(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-21160NCBZ-100
(Rev.:RevD)

SHARC Digital Signal Processor

Analog Devices 

ADSP-21160M/ADSP-21160N

Flags

For flags, see Table 17 and Figure 14.

Table 17. Flags

Parameter

Timing Requirements

tSFI

tHFI

tDWRFI

tHFIWR

FLAG3–0 IN Setup Before CLKIN High1

FLAG3–0 IN Hold After CLKIN High1

FLAG3–0 IN Delay After RDx/WRx Low1, 2

FLAG3–0 IN Hold After RDx/WRx Deasserted1

Min

Max

4

1

10

0

Switching Characteristics

tDFO

tHFO

tDFOE

tDFOD

FLAG3–0 OUT Delay After CLKIN High

FLAG3–0 OUT Hold After CLKIN High

CLKIN High to FLAG3–0 OUT Enable

CLKIN High to FLAG3–0 OUT Disable3

9

1

1

tCK– tCCLK + 5

1 Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.

2 For ADSP-21160M, specification is 12 ns, maximum.

3 For ADSP-21160M, specification is 5 ns, maximum.

Unit

ns

ns

ns

ns

ns

ns

ns

ns

CLKIN

FLAG3–0 OUT

CLKIN

FLAG3–0 IN

RDx

WRx

tDFOE

tDFO

tHFO

tDFO

FLAG OUTPUT

tSFI

tDWRFI

FLAG INPUT

tHFI

tHFIWR

Figure 14. Flags

tDFOD

Rev. D | Page 25 of 58 | September 2015

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