MC141539 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC141539 Datasheet PDF : 29 Pages
| |||
OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER
Description of Block Diagram Module
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data
or command.
Data is directed to this module based upon the input of the D/C pin. If
D/C high, data is written to Graphic Display Data RAM (GDDRAM). D/C
low indicates that the input at D0-D7 is interpreted as a Command.
CE is the master chip selection signal. A High input enable the input
lines ready to sample signals. Reset is of same function as Power ON
Reset (POR). Once RES received the reset pulse, all internal circuitry
will back to its initial status. Refer to Command Description section for
more information.
MPU Parallel Interface
The parallel interface consists of 8 bi-directional data lines (D0-D7),
R/W, and the CS. The R/W input High indicates a read operation from
the Graphic Display Data RAM (GDDRAM). R/W input Low indicates a
write to Display Data RAM or Internal Command Registers depending
on the status of D/C input. The CS input serves as data latch signal
(clock). Refer to AC operation conditions and characteristics section for
Parallel Interface Timing Description.
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to
be displayed. The size of the RAM is determined by number of row
times the number of column (120x32 = 3840 bits). Figure 5 is a descrip-
tion of the GDDRAM address map. For mechanical flexibility, re-map-
ping on both Segment and Common outputs are provided.
Column address 00H
(or column address 77H)
Column address 77H
(or column address 00H)
Row 0
Page 1
Page 2
Page 3
Page 4
Row 31
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
Note : The configuration in parentheses represent the remapping of Commons and Columns
Figure 5. Graphic Display Data RAM (GDDRAM) Address Map
Com0
(Com31)
Com31
(Com0)
MC141539
3–132
MOTOROLA
Share Link: 