LH28F008SC View Datasheet(PDF) - Sharp Electronics
Part Name
Description
Manufacturer
LH28F008SC Datasheet PDF : 38 Pages
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8M (1M × 8) Flash Memory
LH28F008SC
ALTERNATIVE CE » - Controlled Writes1 (Continued)
VCC = 5 V ± 0.5 V, 5 V ± 0.25 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
LH28F008SC-856 LH28F008SC-907 LH28F008SC-1207
UNIT NOTE
MIN. MAX. MIN. MAX. MIN. MAX.
tAVAV Write Cycle Time
85
90
120
ns
tPHEL
RP » High Recovery to
CE » Going Low
1
1
1
µs
2
tWLEL
WE Setup to CE »
Going Low
0
0
0
ns
tELEH CE » Pulse Width
50
50
50
ns
tPHHEH
RP » VHH Setup to CE »
Going High
100
100
100
ns
2
tVPEH
VPP Setup to CE »
Going High
100
100
100
ns
2
tAVEH
Address Setup to CE »
Going High
40
40
40
ns
3
tDVEH Data Setup to CE» Going High 40
40
40
ns
3
tEHDX Data Hold from CE» High
5
5
5
ns
tEHAX Address Hold from CE» High
5
5
5
ns
tEHWH WE Hold from CE» High
0
0
0
ns
tEHEL CE » Pulse Width High
25
25
25
ns
tEHRL CE » High to RY »/BY» Going Low
90
90
90
ns
tEHGL Write Recovery before Read
0
0
0
µs
tQVVL
VPP Hold from Valid SRD,
RY »/BY » High
0
0
0
ns 2, 4
tQVPH
RP » VHH Hold from Valid SRD,
RY »/BY » High
0
0
0
ns 2, 4
NOTES:
1. In systems where CE » defines the write pulse width (within a longer WE » timing waveform), all setup, hold, and inactive WE »
times should be measured relative to the CE » waveform.
2. Sampled, not 100% tested.
3. Refer to Command Definitions Table for valid AIN and DIN for block erase, byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP » should be held at VHH) until determination of block erase, byte write,
or lock-bit configuration success (SR.1/3/4/5 = 0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration)
for testing characteristics.
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration)
for testing characteristics.
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