USS-820D View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

USS-820D

USB Device Controller

Agere -> LSI Corporation 

USS-820D

USB Device Controller

Data Sheet, Rev. 4

June 2001

Register Interface (continued)

Special Firmware Action for Shared Register

Bits

Since the USS-820D registers are not bit-addressable

and contain several bits that may be written by either

firmware or hardware (shared bits), special care must

be taken to avoid incorrect behavior. In particular, firm-

ware must be careful not to write a bit after hardware

has updated the bit, but before firmware has recog-

nized the hardware update of the bit.

There are two general cases where this may occur:

1. Direct collision—Firmware does a read-modify-write

sequence to update a register bit, but between the

firmware read and firmware write, hardware

updates the bit. For example, in dual-packet mode,

hardware could update an SBI/SBI1 bit while firm-

ware is simultaneously resetting the same SBI/SBI1

bit. This would cause firmware to miss the fact that

a new transfer has completed.

2. Indirect collision—Firmware does a read-modify-

write sequence to update a register bit, but between

the firmware read and firmware write, hardware

updates a different bit in the same register. For

example, firmware could do a read-modify-write to

update the SOFODIS bit of the SOFH register, but

at the same time, hardware could be updating the

ASOF status bit. Firmware would inadvertently

reset the ASOF bit without being aware of the hard-

ware update.

These problems can be avoided through the use of the

PEND register, which can only be written by firmware.

Firmware must ensure that the PEND register bit is set

before writing any registers that contain shared bits.

All shared register bits have two copies: a standard

copy and a pended copy. The manner in which these

register bits are updated varies depending on the value

of the PEND register bit, as described in Table 8. The

standard copy is the bit that is read and written during

normal operation (PEND = 0). While PEND = 1, hard-

ware updates only affect the pended copy, and firm-

ware updates only affect the standard copy. When

firmware resets the PEND bit, the pended copies of the

shared bits are used to update the standard copies of

the shared bits as described in Table 9. Through these

means, hardware updates during a firmware read-

modify-write sequence will not be missed.

Table 8. Shared Register Bit Update Behavior

(ASOF Example)

Bit

ASOF

(standard

copy)

ASOF

(pended

copy)

Update

Behavior

While

PEND = 0

Update

Behavior

While

PEND = 1

Updated by Updated by

hardware

firmware

(firmware

must not write

this register)

Not used

Updated by

hardware

Update

Behavior

When

Firmware

Resets

PEND to 0

Updated as

docu-

mented in

Table 9

No longer

used

Firmware must execute the following sequence when

processing a shared bit (to avoid the direct collision

case), or when writing a bit which resides in a register

that contains shared bits (to avoid the indirect collision

case):

I Set the PEND bit.

I Read the register with the shared bit [Read].

I If processing a shared bit, respond to the shared bit.

For example, for an SBI/SBI1 bit, process any data

sets present for that endpoint.

I Update the bit [Modify].

I Write the register with the shared bit with the modi-

fied data [Write].

I Reset the PEND bit.

When a data set is written to a receive FIFO, that

FIFO’s SBI/SBI1 register bit will set. Firmware must

process the indicated receive data set and, in doing so,

manage that FIFO’s SBI/SBI1 bit according to the

sequence described in this section. In dual-packet

mode, it is possible that a second data set will be

written to a receive FIFO before firmware has

completed processing of the initial data set. This

second data set could have been written either before

or after firmware set the PEND bit to 1. Therefore, firm-

ware cannot determine whether or not this second

receive done indication was saved in the pended copy

of the SBI/SBI1 bit. Because of this uncertainty, firm-

ware must process all receive data sets which are

present in the indicated FIFO before resetting the

PEND bit to 0. If the receive done indication of the

second data set was in fact saved in the pended SBI/

SBI1 register, then the standard copy of the SBI/SBI1

bit will be set when firmware resets the PEND bit to 0.

14

Agere Systems Inc.

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