USS-820D View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

USS-820D

USB Device Controller

Agere -> LSI Corporation 

Data Sheet, Rev. 4

June 2001

USS-820D

USB Device Controller

Register Interface (continued)

In this case, the SBI/SBI1 bit will be set even though

there is no corresponding data set present in the

receive FIFO. Therefore, firmware must be prepared to

service a receive done interrupt where no data sets are

present in the indicated FIFO.

Table 9 shows the values loaded into each of the stan-

dard copies of the shared register bits when firmware

resets the PEND register bit.

Table 9. Shared Register Update Values When

Firmware Resets PEND

Register Bit(s)

Update Value

SBI

All bits Set to 1 if standard copy = 1 or

pended copy = 1.

SBI1

All bits Set to 1 if standard copy = 1 or

pended copy = 1.

RXSTAT RXSETUP Loaded with pended copy if

USB action updated RXSETUP

while PEND was set.

RXSTAT EDOVW Set to 1 if standard copy = 1 or

pended copy = 1.

EPCON RXSTL Set to 1 if standard copy = 1 or

pended copy = 1.

SOFH

ASOF Set to 1 if standard copy = 1 or

pended copy = 1.

SOFH

TS Loaded with pended copy if

USB SOF was received while

PEND was set.

SOFL

All bits

Loaded with pended copy if

USB SOF was received while

PEND was set.

SSR

RESET Set to 1 if standard copy = 1 or

pended copy = 1.

The register bits that are only updated by firmware, but

reside in registers with shared bits and must therefore

be updated only while PEND is set, are shown in

Table 10.

Table 10. Register Bits Only Updated While PEND

is Set

Register

RXSTAT

EPCON

SOFH

SSR

Bit(s)

RXSEQ

All bits except RXSTL

SOFIE, SOFODIS

SUSPPO, SUSPDIS, RESUME,

SUSPEND

Firmware should attempt to minimize the period during

which PEND is set in order to minimize the distortion of

the detection of hardware events.

Register Reads with Side Effects

In general, USS-820D register reads do not have side

effects—they do not cause any device state to change.

The following are exceptions to this rule:

I RXDAT reads cause the internal RX FIFO read

pointer to change and possibly cause the

RXFLG.RXURF register bit to set.

I RXCNTH/RXCNTL reads while RXFLG.RXFIF = 00

cause the RXFLG.RXURF register bit to set.

I LOCK reads restart the register unlock sequence

after suspend (described in Special Action Required

by USS-820/USS-825 After Suspend—AP97-

058CMPR-04).

I Any register reads during a register unlock sequence

after suspend, other than the LOCK register, cause

the unlock sequence to fail and require the sequence

to be restarted.

Agere Systems Inc.

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