USS-820D View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

USS-820D

USB Device Controller

Agere -> LSI Corporation 

USS-820D

USB Device Controller

Data Sheet, Rev. 4

June 2001

Register Interface (continued)

Table 14. Serial Bus Interrupt 1 Register (SBI1)—Address: 15H; Default: 0000 0000B

This register contains the USB function’s transmit and receive done interrupt flags for nonisochronous endpoints.

These bits are never set for isochronous endpoints.

Bit 7

FRXD7

Bit 6

FTXD7

Bit 5

FRXD6

Bit 4

Bit 3

FTXD6

FRXD5

R/W (S*)

Bit 2

FTXD5

Bit 1

FRXD4

Bit 0

FTXD4

Bit

Symbol

Function/Description

7

FRXD7 Function Receive Done Flag, Endpoint 7.

6

FTXD7 Function Transmit Done Flag, Endpoint 7.

5

FRXD6 Function Receive Done Flag, Endpoint 6.

4

FTXD6 Function Transmit Done Flag, Endpoint 6.

3

FRXD5 Function Receive Done Flag, Endpoint 5.

2

FTXD5 Function Transmit Done Flag, Endpoint 5.

1

FRXD4 Function Receive Done Flag, Endpoint 4.

0

FTXD4 Function Transmit Done Flag, Endpoint 4.

* S = shared bit. See Special Firmware Action for Shared Register Bits section.

For all bits in the interrupt flag register, a 1 indicates that an interrupt is actively pending; a 0 indicates that the inter-

rupt is not active. The interrupt status is shown regardless of the state of the corresponding interrupt enable bit in

the SBIE/SBIE1.

Hardware can only set bits to 1. In normal operation, firmware should only clear bits to 0. Firmware can also set the

bits to 1 for test purposes. This allows the interrupt to be generated in firmware.

A set receive bit indicates either that valid data is waiting to be serviced in the RX FIFO for the indicated endpoint

and that the data was received without error and has been acknowledged, or that data was received with a receive

data error requiring firmware intervention to be cleared.

A set transmit bit indicates either that data has been transmitted from the TX FIFO for the indicated endpoint and

has been acknowledged by the host, or that data was transmitted with an error requiring firmware intervention to be

cleared.

If TXNAKE = 1, this also may indicate that a NAK was sent to the host in response to an IN packet that was

received when TXFIF = 00. This condition also sets TXVOID. This SBI/SBI1 setting will persist until firmware clears

TXVOID (or clears TXNAKE).

18

Agere Systems Inc.

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